Market-leading Hardw are/Softw are Co-Verification
Seamless for Field Programmable SoC n FPSoC devices share many of the same challenges of the SoC and Board methodologies they will replace: — Hardware & Software - must be developed and verified together — Controllability & Observability - gaining access to all the signal & processor information, pre-silicon & post silicon playback — Early Availability - designing 1M+ gates is a lengthy process - how soon can you start software debug? — System Considerations - most systems will contain devices (memories, co-processors, etc) outside the FPSoC 2 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Hardware/Software Co-Verification n Seamless Hardware/Software Co-Verification provides a Virtual Prototyping environment that enables early, productive debug of complex embedded systems Early Availability n Controllability n — stop clock CPU Timer & Unique Watchdog Core — single step Value-Add — “ what if? ” analysis Hardware Device-1 Driver RTOS Observability Device-2 Driver n Device-3 Driver — all signals, all Unique internals available Peripheral Peripheral Value-Add Ease of change n Software Memory Peripheral Ease of debug n Performance profiling n 3 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Virtual Prototyping: Logic Simulation Logic simulation can: n — show how hardware responds to software — model interrupts, resets, other events that effect software — show how hardware timing can impact software execution — give access and trace of any signal or node in the design — allow ‘ what if ’ analysis of hardware events Simulation can not: n — give visibility of processor or memory internals — show ‘ C ’ or assembly code — show how software responds to hardware stimuli — simulate sufficient code 4 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Virtual Prototyping: Software Simulation Software (Instruction Set) Simulation n can: — view code, registers, memory — step through code — show how software reacts to hardware Software Simulation can not: n — model clocks — model external hardware — model interrupts, exceptions, resets — show bus contention, protocol violations, timing issues 5 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Virtual Prototyping: Hardware/Software Co-Verification Combining software + hardware simulation gives all the benefits n & removes restrictions 6 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Debug/Flow Control in Co-Verification XRAY ModelSim Seamless Coherent Memory Server Controls the flow of data from ISS to Logic Simulator (& back) n Without optimizations, all cycles are routed through logic n simulator Full debug of all logic & software events n Can drive both environments from single location n 7 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Optimizing Co-Verification Performance Optimized Fetches, Stores & Loads Non-Optimized Memory Requests Coherent Memory Server “ Instruction Fetch & Memory Access ” Optimization n Some or all memory accesses routed direct to memory server n — User specifies which and when Clock cycles driven to logic simulator n 8 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Optimizing Co-Verification Performance Optimized Fetches, Stores & Loads Non-Optimized Memory Requests Coherent Memory Server “ Time ” Optimization n Some or all memory accesses routed direct to memory server n — User specifies which and when Clock cycles NOT driven to logic simulator n 9 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Optimizing Co-Verification Performance n Optimization Controlling — Through the Seamless GUI n switch optimizations on/off n define optimization ‘ recipes ’ — Through the Logic Simulator n associate Seamless commands with hardware events — Through the Debugger n associate Seamless commands with software states or events 10 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Seamless with Excalibur: Current Status Stripe Get the Stripe Netlist n Dual-Port DPRAM for Seamless : RAM Interface — Insert ARM922T PSP — Use Seamless SRAM Compatible Memories (Single Port) PLD SDRAM SDRAM Create Seamless n Interface Controller Bridge Configuration File Flash Master Port EBI Interface Slave Port — Describe to Seamless how to invoke the ISS PLLs ARM922T & load the software — Define the memory map & configuration EPXAx Run Co-Verification n 11 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Seamless with Excalibur: Solution Stripe “ Super PSP ” Delivery n Dual-Port DPRAM from Mentor Graphics RAM Interface including: SRAM — Excalibur stripe netlist (Single Port) ready to use with PLD Seamless : SDRAM SDRAM Interface Controller Bridge n ARM922T PSP Flash Master Port EBI n Seamless-ized Interface Slave Port memory models PLLs ARM922T — Scripts to read configuration registers to automatically generate Seamless Configuration File 12 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Seamless ARM922 PSP ARM922t r0 == ARM920t r1 with 8KB I/D Caches n Based on high-performance, cycle accurate co- n verification Model from ARM Supports XRAY, ADU and ARMSD debuggers n Interface to ModelSIM, and all popular Verilog n and VHDL simulators Integrated with 3rd party tools (e.g. Verisity n SpecMan Elite) Seamless VHDL/Verilog Pin Wrapper Instruction Set Simulator (ISS) – Complete instruction set – Registers BUS Interface Model (BIM) – Peripherals – InterruptReset – Bus Cycle Timing – Instruction Timing – Controllers (DMA, MMU, Cache … ) Coherent Memory Server 13 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
ARM Cores Support n Mentor Graphics continues to be the leading supplier of ARM processor co-verification models — ARM7 ™ Family — ARM9 ™ Family — ARM9E ™ Family — ARM10 ™ Family — ARM Jazelle Technology ™ Family 14 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Seamless with C-Bridge n Extend co-verification to reach C-based prototyping and accelerated verification — Support for integration of ‘ C ’ models — Enables rapid prototyping of functionality & performance — Earlier verification at higher abstraction — Single language to refine into either HW or SW n Provide API to support all popular dialects of C — Anything that exposes a C interface and whose interface can be expressed in a dataflow, cycle or event semantics — Support ANSI C, SystemC and CynLib models 15 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Seamless With C-Bridge HDL Design Application SW New New CPU CPU DSP DSP DSP DSP HW HW Core Core Core Core Core Core IP IP IP IP Mem CPU CPU CPU CPU CPU CPU Glue Glue Glue Glue Mem CPU CPU Cont. . Perif. Perif Perif. . . Perif. Perif Perif. . . Logic Logic Logic Cont Perif Perif Logic I/O Memory Memory I/O I/O I/O ‘ C ’ HW .dll Coherent Pins Memory Server C C Host Host C-Bridge C-Bridge Code Code No changes to HDL or SW code Bus Access API Bus Access API n Debug Debug Use C-Bridge API to interface n New HW New HW Abstract ‘ C ’ Bus C model into design Abstract ‘ C ’ Bus Peripheral Peripheral Load C HW dynamic library n from Seamless configuration file Optional connection of control pins n 16 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
Seamless Co-Verification Summary n Virtual Prototyping — provides a flexible, controllable environment for the design and debug of complex systems n Seamless Hardware/Software Co-Verification — links together hardware and software simulation environments into an effective Virtual Prototype n Seamless / Excalibur Integration — allows Excalibur users to rapidly create Seamless configuration file and to focus on the validation of their original SW against their original HW 17 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
For More Product Information n www.mentor.com/seamless n seamless_info@mentor.com n Customers Successes : www.mentor.com/seamless/cust_successes — Alcatel : “ Altera FPGA Platform Evaluation Using Seamless ” n Seamless Technical Workshops — Request a workshop in your area @ www.mentor.com/seamless/workshops/description.html 18 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
19 SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential
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