Main Memory Table of contents 1. History 2. Serial number of - PowerPoint PPT Presentation

Main Memory

Table of contents 1. History 2. Serial number of memory 3. Principles of Operation

Table of contents 1. History 2. Serial number of memory 3. Principles of Operation

Magnetic core memory(1947 ～ 1960s) ・ Stored information by means of a magnetic ferrite core on the small ring. ・ In order to stored with magnetic, the content does not disappear when the power off.

Magnetic core memory(1950 ～ 1960s) Problem: ・ Difficult to miniaturization and Speed. ・ destroyed memory contents. - Interference in each other’s magnetic cell. - Noise when power on. semiconductor memory (Semicondocutor Rondom Access Memory)

RAM(Ramdom Access Memory)(1970’s ～ ) ・ Can read and write Operation to the address of any memory cell. ・ Volatile memory. Semiconductor RAM Static RAM Dynamic RAM

SRAM:Static RAM ・ SRAM have been configured Sequential circuit by transister. WordLine P Read Write DataLine

DRAM:Dynamic RAM ・ Known as stored in the capacitor changes the capacitor and this charge by the presence of bits of information to remember. ・ Need to “refresh”. Wordline Internal data lines

Comparison of SRAM and DRAM SRAM DRAM Structure Complex Simple Integration Low High Capacity Small Large Per bit High Low Strage system Flip Flops Capacitors Speed Fast Slow

Early DRAM(1970 - 1980s) ・ No widely adopted standard operation, DRAM needed to verify the detailed specifications for product. ・ We did have to use the each memory for each PC. made in IBM made in IBM memory memory IBM PC HP PC

DRAM problems ・ DRAM is the address you specify two rounds, so slow access. ・ Refresh is not related to Lead / Write, heavy burden to the microprocessor.

SDRAM:Synchronous DRAM(1990 - 2000) ・ The clock can be synchronized to any external interface, read / write access times and immobilization, which enabled high speed operation. ・ Burst transmission - Only to single address, We can continuous transfer of data of following the address. Became possible to transfer data faster.

SDRAM(1990 - 2000) ”SDRAM more quickly?” ・ semiconductor process does not progress rapidly. ・ Limit to improve internal clock of SDRAM. DDR-SDRAM (Double Data Rate SDRAM)

DDR-SDRAM:Double Data Rate-SDRAM(2001 - 2005) ・ Data exchange to memory cell is parallel Processing. Fetch two word Transfer one word per clock per half clock

DDR2(2004 -) ・ DDR2 is two times the internal interface on DDR1, that is provided with four line was extended to this structure. ・ DDR2 is, DDR1 external interface of the two used as the input clock frequency times the internal interface that is how it is using two clock dividers. (1) Fetch four word Transfer one word per per clock half clock by two times of (1)

DDR3(2007 -) ・ Twice the internal interface of the DDR2. ・ The operating voltage was reduced from 1.8 v to 1.5 v. (1) Transfer one word per Fetch 8 word half clock by 4 times of (1) per clock

DDR4(201x ~)? ・ Twice the internal interface of the DDR3....? ‘Slow version DDR4’ ・ Likely to be adopted signal of differential method? ‘High-speed version DDR4’

Serial number of memory

If you buy memory. You must check Memory spec 2GB Transcend DDR3‐1066 240P UB‐DIMM Module Size:2GB Memory ModulePackage:240‐Pin DIMM • Desktop Memory Feature:DDR3‐1066 ‐ PC3‐8500 memory moduleSpecs:DDR3‐1066 • PC3‐8500 • Non‐ECC •1.5V • SDRAM • CL7

Memory Specs PC3‐8500 DDR3 SDRAM (DDR3‐1066) 2GB 240‐pin JEDEC buffered non‐ECC CL=7

Memory name Module name DDR3‐1066 PC3‐8500 Transfer rate clock frequency 8500MB/s 1066M bit/s 1B(Byte)= ８ bit

Standard of memory DDR3 SDRAM (Double‐Data‐Rate Synchronous Dynamic Random Access Memory) Capacity of memory 2GB 240pin

DDR1 DDR‐1 DIMMs require 184 pins instead of the 168 pins used by standard SDRAM DIMMs. DDR‐1 is versaVle enough for use in desktop PCs or servers. To vary the cost of DDR‐1 DIMMs for these different markets, memory manufacturers provide unbuffered and registered versions. Unbuffered DDR‐1 DIMMs place the load of all the DDR modules on the system memory bus. They can be used in systems that do not require high memory capacity. Registered DDR‐1 DIMMs place only one load per DIMM on the memory bus, regardless of how many SDRAM devices are on the module. Therefore, they are best suited for servers with very high memory capaciVes.

DDR2 DDR‐2 SDRAM is the second generaVon of DDR SDRAM. It offers data rates of up to 6.4 GB/s, lower power consumpVon, and improvements in packaging. At 400 MHz and 800 Mb/s, DDR‐2 increases memory bandwidth to 6.4 GB/s—800 percent more than original SDRAM. DDR‐2 SDRAM achieves this higher level of performance and lower power consumpVon through faster clocks, 1.8‐V operaVon and signaling, and simplificaVon of the command set. The 240‐pin connector on DDR‐2 is needed to accommodate differenVal strobes signals.

DDR2 Memory Memory name I/O Bus Speed Module name DDR2‐400 200 MHz PC2‐3200 DDR2‐533 266 MHz PC2‐4200 DDR2‐667 333 MHz PC2‐5300 DDR2‐800 400 MHz PC2‐6400 DDR2‐1066 533 MHz PC2‐8500

DDR3 DDR‐3, the third‐generaVon of DDR SDRAM technology, makes further improvements in bandwidth and power consumpVon. Manufacturers of DDR‐3 started with 90 nm fabricaVon technology and are moving toward 70 nm as producVon volumes increase. DDR‐3 operates at clock rates from 400 MHz to 800 MHz with theoreVcal peak bandwidths ranging from 6.40 GB/s to 12.8 GB/s. DDR‐3 DIMMs can reduce power consumpVon by up to 30 percent compared to DDR‐2 DIMMs operaVng at the same speed. DDR‐3 DIMMs use the same 240‐pin connector as DDR2 DIMMs, but the notch key is in a different posiVon

DDR3 Memory Memory name I/O Bus Speed Module name DDR3‐800 400 MHz PC3‐6400 DDR3‐1066 533 MHz PC3‐8500 DDR3‐1333 667MHz PC3‐10600 DDR3‐1600 800MHz PC3‐12800

Unbuffered or Registerd To achieve higher memory subsystem capacity, some DIMMs have register logic chips (registers) that act as a pass‐through buffer for address and command signals. Registers prevent the memory controller from having to drive the enVre arrangement of DRAM chips on each module. Rather, the memory controller drives only the loading of the registers on each module. The register on each DIMM re‐drives the address and command signals to the appropriate DRAM chip. Simultaneously, a phase lock loop chip on the registered DIMM generates a second clock signal that runs synchronously with the system bus clock and eliminates the need for the system bus clock signal from having to drive all the DRAM chips. It also allows adding more memory modules to the memory bus to increase memory capacity.

ECC or Non‐Ecc error correcVon code (ECC) memory Parity checking detects only single‐bit errors. It does not correct memory errors or detect mulV‐bit errors.

JEDEC ( Joint Electron Device Engineering Council ) JEDEC is the leading developer of standards for the solid‐state industry. Almost 3,300 parVcipants, appointed by some 300 companies work together in 50 JEDEC commibees to meet the needs of every segment of the industry, manufacturers and consumers alike. The publicaVons and standards that they generate are accepted throughout the world. All JEDEC standards are available online, at no charge. JEDEC planning standards of SDRAM and DIMM, and a lot of the other. JEDEC compliance give assurance a quality of memory.

Principles of Opera/on

DRAM (1) • Main memory consists of DRAM chips on dual inline memory modules (DIMMs) that can be packaged in various ways depending on system form factor. DRAM DIMM

DRAM (2) • Each DRAM chip contains millions of memory locations or cells. • A charged cell represents a “1” data bit, and an uncharged cell represents a “0” data bit.

DRAM (3) • Memory writes data – First selects the page by strobing the Row Address(RAS) onto the address/command bus. – It then selects the exact loca/on by strobing the Column Address (CAS)onto the address/command bus.

DRAM (4) • During a DRAM read opera/on, RAS Column Address S ignal (CAS) followed by CAS are driven onto the memory bus. • The WE signal is held inac/ve, Row Address signal (RAS) indica/ng a read opera/on. ANer a delay called CAS Latency, the DRAM devices drive the data onto the memory bus. • DRAM cannot be accessed during a refresh.

Write Opera/on transistor transistor Capacitor charge Capacitor discharge Write [1] Write [0] • The voltage of the bit line is raised with the voltage in the word line raised to write “ 1 ” in the memory cell, and the capacitor is charged through the transistor. • Through the transistors, capacitors from charging the bit line, which made the charge accumulation “ 1 ” is written. • The “ 0 ” to write the bit-line voltage is raised while the word line voltage 0 V and to discharge the charge stored in the capacitor through the transistor.