Low-Power RF Integrated Circuit Design Techniques for Short-Range - - PowerPoint PPT Presentation

▶
low power rf integrated circuit design techniques for
SMART_READER_LITE
LIVE PREVIEW

Low-Power RF Integrated Circuit Design Techniques for Short-Range - - PowerPoint PPT Presentation

Jun 18, 2023 278 likes •572 views

Low-Power RF Integrated Circuit Design Techniques for Short-Range Wireless Connectivity Marvin Onabajo Assistant Professor Analog and Mixed-Signal Integrated Circuits (AMSIC) Research Laboratory Dept. of Electrical and Computer Engineering

slide-1
SLIDE 1

Low-Power RF Integrated Circuit Design Techniques for Short-Range Wireless Connectivity

Marvin Onabajo

Assistant Professor Analog and Mixed-Signal Integrated Circuits (AMSIC) Research Laboratory

  • Dept. of Electrical and Computer Engineering

Northeastern University, Boston, USA Email: monabajo@ece.neu.edu Website: www.ece.neu.edu/~monabajo

ES2 Northeastern University Planning Grant Meeting November 30, 2017

slide-2
SLIDE 2

AMSIC Research Lab

Outline

  • Introduction

– Motivation for low-power RF CMOS circuit design – Technical challenges

  • Linearity improvement method for subthreshold

low-noise amplifiers

– Theory and simulation – Measurement results

  • Integrated RF front-end chip

– Low-noise amplifier and mixer – Measurement results

  • Conclusions

2

slide-3
SLIDE 3

AMSIC Research Lab

Health Monitoring Application Example: Wireless Body Area Network (WBAN)

 Circuit design challenges (in addition to performance, size, reliability, cost)

Reduction of power consumption to extend battery lifetime

Resilience to interference signals

3

slide-4
SLIDE 4

AMSIC Research Lab

  • Power efficiency

→ Higher transconductance-to-drain

current (gm/ID) ratio than in the strong inversion region → Suitable for low supply voltages

  • Lower transition frequency

(ωT ≈ gm/Cgg)

  • Capacitance Cgs does not dominate

in the subthreshold region

→ Other parasitic capacitances (Cgd and Cgb) should be carefully taken into account

Subthreshold RF Design Considerations

4

slide-5
SLIDE 5

AMSIC Research Lab

Subthreshold RF Design Considerations (cont.)

3 3 2 2 1 gs gs gs d

v g v g v g i      

For a weakly nonlinear transconductance amplification stage:

where: g1 = gm (linear transconductance gain) g2 and g3 are the 2nd-order and 3rd-order nonlinearity coefficients

3 3 3 2 2 2 1

6 1 , 2 1 ,

GS GS

V I g V I g V I g

D D GS D

          

  • Subthreshold linearity characteristics

→ Sign change of g3/g1 → High g3/g1 ratio (signal distortion)

5

slide-6
SLIDE 6

AMSIC Research Lab

Z3

Linearized Subthreshold Low-Noise Amplifier (LNA)

  • 3rd-order nonlinearity (distortion) cancellation

– Without active components → minimization of power consumption – No cross-coupling is required → permits the use of a single-ended architecture

C.-H. Chang and M. Onabajo, “Linearization of subthreshold low-noise amplifiers,” in Proc. IEEE Intl.

  • Symp. on Circuits and Systems (ISCAS), pp. 377-380, May 2013.

6

slide-7
SLIDE 7

AMSIC Research Lab

Z3

3rd-Order Intermodulation Intercept Point (IIP3)

where: Analysis result:

) 2 , ( ) ( ) ( 6 1

3 1 3

          A H R IIP

s

  • B

g g   

3

) 2 , (               ) 2 ( 1 ) ( 2 3 2

1 1 2 2

  g g g g g goB

   

) ( ) ( ) ( ) ( ) ( 1 ) (

1 1 3 1 1

       

x x gs gd

Z Z Z C j Z Z C j g     

               ]

[

3 2 3 1 2 1 1 2

         Z Z Z Z Z Z C j Z Z

gd x

       

7

slide-8
SLIDE 8

AMSIC Research Lab

IIP3 Evaluation with Various Lg2 and Cgd2_ext Values

8

slide-9
SLIDE 9

AMSIC Research Lab

Chip Micrographs of Fabricated Linearized Subthreshold LNAs

(a) Dongbu 0.11μm CMOS technology

C.-H. Chang and M. Onabajo, “Low-power low-noise amplifier IIP3 improvement under consideration

  • f the cascode stage,” in Proc. IEEE Intl. Symp. on Circuits and Systems (ISCAS), May 2017.

(b) IBM 0.13μm CMOS technology (a) “Work 1” (b) “Work 2”

9

slide-10
SLIDE 10

AMSIC Research Lab

LNA Printed Circuit Board with IIP3 Tuning Functionality

10

slide-11
SLIDE 11

AMSIC Research Lab

Comparison with Other Subthreshold LNAs

Reference Work 1+ Work 2+ [1]+ [2]+ [3]# [4]$ [5]§ fc [GHz] 1.8 2.1 2.4 3 1 2.4 1 S21 [dB] 14.8 9 21.4 4.5 13.6 13.1 16.8 NF [dB] 3.7 5.8 5.2 6.3 4.6 5.3 3.9 IIP3 [dBm]

  • 3.7
  • 11
  • 10.5

7.2

  • 12.2
  • 11.2

P1dB [dBm]

  • 12.6
  • 8.4
  • 15
  • 19.5

0.2

  • 19
  • 21

PDC [μW] 336 300 1134 156 260 60 100

  • Tech. [μm]

0.11 0.13 0.18 0.13 0.18 0.13 0.18 Layout [mm2] (# of Ind.) 0.624 (3) 0.24 (3) 0.717 (1) 2.0 (4) 0.694 (3) 0.63 (2) 0.809 (1) FOM 9.7 8.5

  • 0.7
  • 0.5

17.1

  • 6.6

5.6

+ measured in package (cascode topology) # probe measurements (single-transistor topology) $ measured in package (self-biased inverter topology) §measured in package (inductive feedback topology)

              ] [ ) 1 ] [ ( ] [ ] [ 3 ] [ log 10 mW PD abs NF GHz f mW IIP abs Gain FOM

11

slide-12
SLIDE 12

AMSIC Research Lab

References

[1] A. V. Do, C. C. Boon, M. A. Do, K. S. Yeo, and A. Cabuk, “A subthreshold low-noise amplifier optimized for ultra-low-power applications in the ISM band,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 2, pp. 286-292,

  • Feb. 2008.

[2] H. Lee and S. Mohammadi, “A 3GHz subthreshold CMOS low noise amplifier,” in

  • Proc. Radio Frequency Integrated Circuits (RFIC) Symp., June 2006.

[3] B. G. Perumana, S. Chakraborty, C.-H. Lee, J. and Laskar, “A fully monolithic 260- μW, 1-GHz subthreshold low noise amplifier,” IEEE Microwave Theory and Wireless Component Letters, vol. 15, no. 6, pp. 428 - 430 , June 2005. [4] T. Taris, J. Begueret, and Y. Deval, “A 60μW LNA for 2.4 GHz wireless sensors network applications,” in Proc. Radio Frequency Integrated Circuits (RFIC) Symp., June 2011. [5] A. Shameli and P. Heydari, “A novel ultra low power low noise amplifier using differential inductor feedback,” IEEE European Solid State Circuit Conference (ESSCIRC), Sep. 2006, pp. 352-355.

12

slide-13
SLIDE 13

AMSIC Research Lab

Low-Power RF Front-End

 Combined LNA & mixer to

demonstrate the compatibility of the linearization techniques

 Proof-of-concept measurements

  • L. Xu, C.-H. Chang, and M. Onabajo, “A 0.77mW 2.4GHz RF front-end with -4.5dBm in-band IIP3 through inherent

filtering,” IEEE Microwave and Wireless Components Letters (MWCL), vol. 26, no. 5, pp. 352-354, May 2016. 13

slide-14
SLIDE 14

AMSIC Research Lab

Die Micrograph of the RF Front-End (0.13μm CMOS Technology)

14

slide-15
SLIDE 15

AMSIC Research Lab

Measurement Setup

Measured voltages at the intermediate frequency (IF) outputs Simulated voltages at the IF outputs 15

slide-16
SLIDE 16

AMSIC Research Lab

Performance Summary and Comparison

16

slide-17
SLIDE 17

AMSIC Research Lab

References

[6] A. Selvakumar, M. Zargham, and A. Liscidini, “Sub-mW Current Re-Use Receiver Front-

End for Wireless Sensor Network Applications,” IEEE J. Solid-State Circuits, vol. 50, no. 12, Dec. 2015.

[7] Z. Lin, P.-I. Mak, and R. P. Martins, “A 0.14-mm2 1.4-mW 59.4-dB-SFDR 2.4 GHz

ZigBee/WPAN Receiver Exploiting a Split-LNTA + 50% LO topology in 65-nm CMOS,” IEEE Trans. on Microwave Theory and Techniques, vol. 62, no. 7, pp. 1525-1534, Jul. 2014.

[8] Z. Lin, P.-I. Mak and R. P. Martins, “A 2.4-GHz ZigBee Receiver Exploiting an RF-to-BB-

Current-Reuse Blixer + Hybrid Filter Topology in 65-nm CMOS,” IEEE J. of Solid-State Circuits, vol. 49, pp. 1333-1344, June 2014.

[9] F. Zhang, K. Wang, J. Koo, Y. Miyahara, and B. Otis, “A 1.6mW 300mV-Supply 2.4GHz

Receiver with -94dBm Sensitivity for Energy-Harvesting Applications,” in Int. Solid-State Circuits Conf. Tech. Dig., pp. 456-457, Feb. 2013.

[10] B. W. Cook, A. D. Berny, A. Molnar, S. Lanzisera, and K. S. J. Pister, “Low-power 2.4-

GHz Transceiver With Passive RX Front-End and 400-mV Supply,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2757-2766, Dec. 2006.

17

slide-18
SLIDE 18

AMSIC Research Lab

Conclusion

  • Subthreshold LNA linearization method to enable low-power design

– Extra inductor and capacitor for nonlinearity cancellation – Negligible impact on power, noise and gain design tradeoffs – IIP3 improvement: 4.8-11.2 dB – 1-dB compression point improvement: 7.1-11.6 dB

  • Linearization techniques for low-power RF front-ends in short-range

wireless communication devices

– Adaptation of the linearization technique for low-power active mixers – Demonstrated with a low-power linearized RF front-end

  • The design methods do not require an auxiliary amplifier circuit

→ Suitable for low-power applications

18

slide-19
SLIDE 19

AMSIC Research Lab

Thank You. Questions are Welcome.

Marvin Onabajo

Analog and Mixed-Signal Integrated Circuits (AMSIC) Research Laboratory

  • Dept. of Electrical and Computer Engineering

Northeastern University, Boston, USA Email: monabajo@ece.neu.edu Website: www.ece.neu.edu/~monabajo The projects were supported in part by the National Science Foundation under awards #1349692 and #1451213.

slide-20
SLIDE 20

AMSIC Research Lab

Appendix ↓

slide-21
SLIDE 21

AMSIC Research Lab

Examples of Low-Power Wireless Communication Standards

Wireless Personal Area Network (WPAN) Wireless Body Area Network (WBAN) Bluetooth Low Energy (BLE) IEEE 802.15.4 (ZigBee) IEEE 802.15.6 Frequency Range 2.4-2.4835 GHz 2.4 GHz, 868 MHz, 915 MHz, 2.4-2.2483 GHz, 2.36-2.4 GHz(US), (400/868/915/950 MHz) Data Rate 1 Mbps 20 Kbps – 250 Kbps 75.9 Kbps – 971.4 Kbps Network Size undefined up to 65536 devices up to 256 devices Range 10-75 m 10-100 m 2-5 m

21

slide-22
SLIDE 22

AMSIC Research Lab

Generalized Linearization Approach

  • Commonly used technique for LNAs: one or more auxiliary amplifiers

to cancel the 3rd-order nonlinearity term of the main amplifier – Main amplifier: typically in strong inversion – Auxiliary amplifier: in strong inversion or weak inversion (depending on the topology)

  • Main drawback: extra power consumption and increased complexity

due to the DC biasing circuitry for the auxiliary amplifier(s)

α3 = α3m+ α3a= 0

22

slide-23
SLIDE 23

AMSIC Research Lab

Z3 Analysis with and without Lg2 and Cgd2_ext

2 2 conv 3

1 ) (

gs m

C j g Z    

Conventional LNA: Linearized LNA: Small-signal equivalent circuit for the second stage (with M2) and load:

23

) )( ( ) ( 1 ) (

2 2 2 2 2 2 2 2 2 2 2 2 2 _ 3 g d gs m gd gs m g d gd gs gd gs d gd Lin

Z Z C j g C j C j g Z Z C C C j C j Z C j Z                 

slide-24
SLIDE 24

AMSIC Research Lab

IIP3 Simulation Results

>11dB IIP3 improvement for input power levels below -35dBm

24

slide-25
SLIDE 25

AMSIC Research Lab

LNA IIP3 vs. Cgd2_ext Comparison (Simulation vs. Measurement Results)

IIP3 vs. tuning code

25

slide-26
SLIDE 26

AMSIC Research Lab

Linearized Subthreshold Mixer

Structure with cross-coupling capacitors (CC)

 Negative capacitance generation to partially cancel the parasitic capacitance at X  Terminal impedances can be adjusted to enhance IIP3  Enables wideband linearization

  • L. Xu, K. Wang, C.-H. Chang, and M. Onabajo, “Inductorless linearization of low-power active mixers,”

in Proc. IEEE Intl. Symp. on Circuits and Systems (ISCAS), pp. 2213-2216, May 2015. 26

M1 Rd RF+ RF- LO+ LO- LO+ IF- IF+ M2 Rd M1 M3 M3 M 2 CC CC X X

slide-27
SLIDE 27

AMSIC Research Lab

Differential Front-End with LNA and Mixer: Measured S11 Parameter, Voltage Conversion Gain and Noise Figure (NF)

27 Voltage gain from the LNA input to mixer output (IF = 10MHz) and S11 vs. frequency Voltage gain and NF vs. LO power

slide-28
SLIDE 28

AMSIC Research Lab

Differential Front-End with LNA and Mixer: Linearity Performance Measurements (IIP3 & IM3)

28

IIP3 of the RF front-end IM3dBc with input power of -31.5dBm (including 10.3dB loss from the buffer stage)