Mixed- -Signals Signals Mixed Integrated Circuit Testing - PowerPoint PPT Presentation

Mixed- -Signals Signals Mixed Integrated Circuit Testing Integrated Circuit Testing Salvador MIR TIMA Laboratory 46 Av. Félix Viallet 38031 Grenoble salvador.mir@imag.fr Montpellier, 27 th March 2007 1

Outline Introduction 1 Analog versus digital testing 2 Structural and functional testing 3 Analogue DFT/BIST techniques 4 Computer-Aided Test (CAT) techniques 5 Conclusions 6 2

Introduction 1 System- -On On- -Board (SOB) Board (SOB) System- -On On- -Chip (SOC) Chip (SOC) System System uP Memory Memory uP digital Mixed RF Signal digital Mixed Signal • Mixed technologies on the same chip • Pre-designed blocks (not tested) • Dedicated technologies • Core and IC level test data • Pre-tested ICs • Board-Level Test 3

Introduction 1 � Accelerometer examples : Self-testable one Self-testable two 4 axis accelerometer axis accelerometer

Introduction 1 � Motivation of mixed-signals testing : � Growth in mixed-signals ICs : efforts to combine analog, digital and memories to provide SoC solutions � Driven by communication and consumer markets � In mixed-signal systems, over 90% is often digital but 90% test cost can be analogue � Communications and biomedical applications are demanding new SoC and SiP devices � Testing mixed-signals devices is very different from digital testing 5

Introduction 1 � What are we testing for ? Physical defects � Cause : process disturbances - Local (silicon defects, photolithography spots …) - Global (mask misalignment, bad micromachining …) � Fault types : - Structural faults : opens, shorts, … - Parametric faults : variations in device parameters have a more important impact on analogue testing � Failures : - Hard (incorrect performance, large performance error) - Soft (marginal out-of-spec performance) 6

Introduction 1 � Production test: quality and economic impact Good device : OK Customer Devices defect to be Pass level tested Bad device : error Tester Good device : error Economic Fail impact Bad device : OK 7

2 Analog versus digital testing � Digital Testing : X1 X2 X3 X4 Y 0 0 0 0 1 ♠ Discrete binary values (0/1) 0 0 0 1 0 0 0 1 0 1 ♠ Truth tables (exact) ♠ Simple parametric testing (e.g. current consumption at wafer level) ♠ Fault-based (structural) or functional testing based on exact logic behaviour at chip and package levels Tolerance In range � Analog Testing : G Nominal ♠ Continuous values behaviour ♠ Differential equations (approx) Out ♠ Specification-based testing fc considering acceptance ranges for design parameters 8

3 Structural and functional testing � Functional testing : � Test matches the Devices functionality to be Pass � Simple test vector tested Specs Pass generation Tester Fail Fail � Typically used for analogue Specs devices but leads to costly test equipment Test program � Lengthy test time due to redundant tests Specifications � Test complexity increases (DC, AC, …) exponentially with device size for digital circuits 9

3 Structural and functional testing � Examples of specification-based tests Y(s)/X(s) Y( ω ) Gdc (+/- 1dB) H1/H2 > 65 dB f f f -3dB (+/- 5%) 10

3 Structural and functional testing � Structural testing : � Tests targeting No faults Devices to structural defects be tested Pass Tester � Based on the use of Fail fault models Faulty � CAD tools for test generation (ATPG, fault Test program simulation) � Does not test exhaustively Test vectors for functionality Fault simulation � Less expensive test Fault model � Typically used for digital devices 11

3 Structural and functional testing � Modeling of catastrophic faults : examples at circuit level D D D M1 L1 G G G R f =1 Ω L R s L2 M2 R f =10 M Ω S MOS Drain-Source short S S MOS Source open MOS Gate-Oxide short Hierarchical faster fault simulation requires the use of higher level Capacitor open Capacitor short (behavioural) fault models 12

4 Analog DFT/BIST techniques � Standards for IC testing: � 1149.1 Standard digital boundary-scan test (1990) – Aims to facilitate observability and controllability of IC signals, in particular transforming very difficult PCB testing problems into well structured ones easily solved by software � 1149.4 Standard Mixed-Signal test bus to be used at device, sub- assembly and system levels (1999) – Aims to increase the observability and controllability of mixed- signal designs and support MS-BIST structures � P1500 Standard test method for embedded cores (working group) – Focused on Standardized Core Test Language (CTL) and configurable & scalable test wrapper for easy core access 13

4 Analog DFT/BIST techniques � BIST Principle � On-chip analogue test signal generation � On-chip analogue test response analysis � Current trends � Enabling each element in an analog chain to be tested independently � Reducing requirement for complex functional tests � Improving test reuse � Exploring the use of digital techniques (as much as possible) for stimulus generation and measurement 14

4 Analog DFT/BIST techniques � BIST relies on accurate mapping of tolerance range specification space signature space mapping of tolerance range • Perfect mapping may not be possible –Objective: minimize misclassification 15

4 Analog DFT/BIST techniques � Histogram (code density) BIST for ADCs : DOUT n AIN ADC selector Test Histogram (code On-chip processor density) calculation periodic test signal ADC static Parameters : generator Offset, Gain DNL, INL Obtained by comparison with ideal histogram 16

4 Analog DFT/BIST techniques � Oscillation BIST Oscillator • Analog CUT plus added circuitry become an oscillator Analog in test mode CUT – Oscillation induced through positive feedback Added • Defects cause deviations in circuitry – Oscillation frequency – Oscillation amplitude Freq. counter 17

4 Analog DFT/BIST techniques � Pseudo-random testing of LTI circuits : pseudo-random test vector signal power spectrum self-testable generator (BILBO register) close to a white noise converter x(j) x(j) AMS LTI AMS LTI Impulse Response IR(k) MLS Gen Gen. . MLS 0.3 ADC y(j) y(j) CUT ADC CUT 0.2 0.1 0 delay by k -0.1 0 10 20 30 40 50 60 h(7) h(7) Correlator Correlator 0.3 0.2 h(k) h(k) 0.1 0 error error Signature Analyzer Analyzer Signature -0.1 0 10 20 30 40 50 60 k − N 1 1 ∑ φ = − ( k ) x ( j k ) y ( j ) Mapping the physical parameter space to xy N = j 0 the IR space; selection of optimal impulse Estimation of the CUT impulse response response samples 18

5 Computer-Aided Test (CAT) � Computer aided testing : � Efficient design and test integration by using Computer- Aided Test (CAT) techniques � Estimation of test metrics and setting of test limits � Efficient determination of test patterns : - optimisation of functional tests - automatic generation of structural tests (ATPG) � ATPG requires : - fault modelling techniques for analogue components - fault simulation of mixed-signal mixed-domain devices and calculation of fault coverage figures 19

5 Computer-Aided Test (CAT) Cadence Database Independency Fault simulation Fault simulation And Fault modeling Fault Simulation Fault modeling Functions reusability FIDESIM Fault injection Fault injection Database Test Evaluation Test Generation Results Test Vectors OPTEVAL OPTEGEN Optimization Algorithms Test evaluation Test evaluation Test vector generation C/C++/Java/… Test vector generation Statistic techniques Statistic techniques Analogue Test vector Analogue Test vector Test metrics estimation codification and optimization Test metrics estimation codification and optimization 20

5 Computer-Aided Test (CAT) � Estimation of test metrics: � It is necessary to work out the relationship between performances and test criteria. The metrics are used in order to set test limits. � Performance Test criterion f S (s) f T (t) Test limit Specification A s B t P(Pass) = P(t ∈ B) P(Functional) = P(s ∈ A) P(Fail) = 1-P(Pass) P(Faulty) = 1-P(Functional) = 1-P(t ∈ B) = 1-P(s ∈ A) 21

5 Computer-Aided Test (CAT) � Estimation of test metrics: � Goal: find the joint Probability Density Function (PDF) between performances and test criteria Y = P(Functional) Y T = P(Pass) Y C = P(Pass/Functional) D = P(Faulty/Pass) = 1-P(Functional/Pass) P PF = P(Pass and Functional) 22

5 Computer-Aided Test (CAT) � Estimation of test metrics using a multi-normal PDF between performances and test criteria Multinormal PDF µ = ( µ 1 , µ 2 , …, µ N ) x = (x 1 , x 2 , …, x N ) Run 1000 Generate millions of Calculate Monte Carlo circuit samples from the multinormal PDF circuit multinormal law parameters ( µ and Σ ) simulations (using Matlab, R, …) 23

5 Computer-Aided Test (CAT) � Setting test limits as a function of test metrics: SNDR [ µ -4.0 σ , µ +4.0 σ ] IDD [ µ -4.1 σ , µ +4.1 σ ] 24

5 Computer-Aided Test (CAT) � CADENCE-based CAT tool for the validation of test strategies 25 Fault modelling, injection and simulation tool Fault modelling, injection and simulation tool