Logic Characteristics of 40 nm Logic Characteristics of 40 nm Logic - PowerPoint PPT Presentation

Logic Characteristics of 40 nm Logic Characteristics of 40 nm Logic Characteristics of 40 nm Logic Characteristics of 40 nm thin thin- -channel channel InAs InAs HEMTs HEMTs Tae-Woo Kim , Dae-Hyun Kim* and Jesús A. del Alamo Microsystems Technology Laboratories MIT *Presently with Teledyne Scientific Sponsors: Intel & FCRP-MSD IPRM June 4 th , 2009 Fabrication: MTL, NSL, SEBL at MIT 1

Scaling issues in III- Scaling issues in III -V HEMT V HEMT  Motivation  III-V HEMT: Model system for future III-V logic FETs  Key dimensions: Gate Gate - Gate Length (L g ) Source Source Source Source Drain Drain Drain Drain - Barrier Thickness (t ins ) Barrier Thickness (t ) Drain Drain L side L side L g L g - Side-recess Length (L side ) Cap Cap - Channel Thickness (t ch ) Barrier Barrier Barrier Barrier t t t ins t ins t ch t ch Channel Channel  Scaling trajectory: - L g ↓  t ins ↓ , t ch ↓ , L side ↓ g ↓ ins ↓ , ch ↓ , side ↓ Buffer Buffer < Schematic of III-V HEMT >  Goal : Explore trade-offs involved in channel thickness p scaling 2

Thin channel Thin channel InAs InAs HEMT HEMT S D L g ~ 40 nm O id Oxide InGaAs/InAlAs L side t ch = 5 nm t ins = 5 nm The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. 6 nm InP The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. L g g 11 11 nm In 0.52 Al 0.48 As I Al A t ins In 0.7 Ga 0.3 As: 1 nm The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. t ch t ch = 5 nm InAs: 2 nm In 0.7 Ga 0.3 As: 2 nm The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. Buffer : In 0.52 Al 0.48 As  n,Hall = 9,950 cm 2 /V-sec T i l Triple-step gate recess process t t Reference : InAs HEMT with t ch = 10 nm - Gate metal stack: Ti/Pt/Au  n,Hall = 13,500 cm 2 /V-sec - L side = 80 nm, t ins = 5 nm <D.-H. KIM IEDM 08> 3

Output & g Output & g m Char.: Char.: L L g = 40 nm = 40 nm t ch = 5 nm InAs HEMT 2.0 t ch = 5 nm InAs HEMT 1.0 t ch = 10 nm InAs HEMT V GS = 0.5 V t ch = 10 nm InAs HEMT L g = 40 nm 1.6 L g = 40 nm 0.8 V GS = 0.3 V S/  m] 1.2 0.6  m ] g m [mS I D [ mA/  0.8 0.4 V GS = 0.1 V 0.4 0.2 V DS = 0.5 V V GS = 0 V 0.0 0.0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6 0.8 V DS [V] V GS [V] - Good I D saturation, pinch-off behavior - g m = 1.65 mS/  m @ V DS =0.5 V 1 65 S/ @ V 0 5 V 4

Subthreshold Char.: Subthreshold Char.: L L g = 40 nm = 40 nm t ch t h = 5 nm InAs HEMT 5 s V DS = 0.5 V 1E-3 t ch = 10 nm InAs HEMT V DS = 0.05 V 1E-4 1E-5 /  m ] 1E-6 1E-6 I D [ A/ Thin ‐ channel HEMTs • Sharper SS 1E-7 • Lower DIBL • Larger I ON /I OFF L I /I 1E-8 L g = 40 nm 1E-9 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 V GS [V] For t ch = 5 nm device at V DS = 0.5 V, SS = 72 mV/dec, DIBL = 72 mV/V and I ON /I OFF = 2.5 x 10 4 5

Subthreshold Char. Subthreshold Char. vs vs L L g L G = 40 nm -3 10 L G = 50 nm L = 70 nm L G = 70 nm -4 10 L G = 80 nm L G = 100 nm -5 10 L G = 150 nm L = 200 nm L G = 200 nm I D [A/  m] -6 10 L g  L g  -7 10 g -8 10 V DS = 0.5 V -9 9 10 10 -0.6 -0.4 -0.2 0.0 0.2 0.4 V GS [V] • Harmonious scaling  Very small V T roll off with L g (34 mV) 6

SS & DIBL vs. SS & DIBL vs. L L g 90 160 In 0.7 Ga 0.3 As HEMT: t ch = 13 nm ng [mV/dec] In 0.7 Ga 0.3 As HEMTs: t ch = 13 nm 80 120 V/V] InAs HEMTs: DIBL [mV InAs HEMTs: btreshold swi t ch = 10 nm t ch = 10 nm 70 80 InAs HEMTs: t ch = 5 nm Su InAs HEMTs: t ch = 5 nm L side = 80 nm, t ins = 5 nm 60 40 40 80 120 160 200 40 80 120 160 200 L g [nm] L g [nm]  Excellent electrostatic integrity and scalability with thin channel <D.-H. KIM IPRM 09> 7

Key trade Key trade- -off: Source resistance off: Source resistance < Gate current injection technique> 0.34 t ch = 13 nm In 0.7 Ga 0.3 As HEMTs t ch = 10 nm InAs HEMTs R sheet = 320 Ohm/sq 0.32 t ch = 5 nm InAs HEMTs 0.30 mm] s [Ohm.m Rs = 0.255 Ohm mm 280 0.28 0.26 240 * R Rs = 0.25 Ohm mm 0.24 Rs = 0.24 Ohm mm 0.22 0 40 80 120 160 200 L g [nm] Thin-channel InAs HEMTs: - Higher R sh  higher R s <D.-H. KIM IPRM 09> 8

Scalability of g Scalability of g mi mi <g mi from S-parameters> 4 4 In 0.7 Ga 0.3 As HEMT: t ch = 13 nm InAs HEMT: t InAs HEMT: t ch = 10 nm 10 nm InAs HEMT: t ch = 5 nm 3 3 3 3 m] g mi [mS/  m V DS = 0.5 V 2 2 40 80 120 160 200 L g [nm] Thin-channel InAs HEMTs: - Lower values of g mi due to lower  n Lower values of g mi due to lower  n - But velocity less affected  better g mi scalability down to 40 nm 9

f T & & f max max char. : char. : L L g = 40 nm = 40 nm 40 1.0 t ch = 5 nm t ch = 10 nm H 21 devices devices f T f 445 GH 445 GHz 520 GH 520 GHz f max 395 GHz 337 GHz V DS = 0.6 V B] U U G V V GS = 0 2 V 0.2 V H 21 & U G [d 20 0.5 L g = 40 nm K H K 0 0.0 1 10 100 1k Frequency [GHz] For thin-channel InAs HEMT: Low f T but high f max 10

Why high Why high f f max max ? ?  Evaluation of g Evaluation of g o 1.0 L g = 40 nm g m] ce [mS/mm 0.8 VDS = 0.5 V InAs HEMT t ch = 10 nm 0.6 onductanc InAs HEMT t ch = 5 nm 0.4 Output co 0.2 InGaAs HEMT t ch = 13 nm 0 0 0.0 0.2 0.3 0.4 0.5 0.6 0.7 I D [mA/mm]  Lower DIBL lower Impact ionization:  Lower DIBL, lower Impact ionization:  improved output conductance with thin channel 11

Unified FOM for Logic Unified FOM for Logic I ON at given I OFF and V DD I ON at given I OFF and V DD 0.5 I OFF = 100 nA/  m V DD = 0.5 V InAs HEMTs: t ch = 5 nm m] I ON [mA/  m InAs HEMTs: 0.4 t ch = 10 nm In 0 7 Ga 0 3 As HEMTs: 0.7 0.3 I t ch = 13 nm 32 nm CMOS 0 3 0.3 10 100 L g [nm] For thin channel InAs HEMT: For thin-channel InAs HEMT:  Better scalability in sub – 100nm regime 12

Conclusion Conclusion • Thin-channel (t ch = 5 nm) InAs HEMTs – At L g = 40 nm, thin-channel HEMTs are excellent g DIBL = 72 mV/V, S = 72 mV/dec and I ON /I OFF > 10 4 • – Main advantage: improved electrostatics and scalability Trade-offs:  n = 9,950 cm 2 /V-sec, R s = 0.255 Ω ·mm – T d ff 9 950 2 /V R 0 255 Ω • • Future work: Future work: – Increase gate foot stem height ~ 200 nm to improve f T – Extract injection velocity and gate capacitance. Extract injection velocity and gate capacitance. – Optimize barrier to lower R s and R C . 13