Living with Uncertainty Jim Dodrill ARM 1 We want our variation - PowerPoint PPT Presentation

Living with Uncertainty Jim Dodrill ARM 1

We want our variation models to be: Effective Efficient Accurate Enough 2

Stage-Based OCV § The dependence of the derate on input transition time and output load is not captured § This will be addressed by adopting LVF as soon as it is practical sigma slew load 3

Voltage Variation § Voltage variation accounts for about half of the derate § Even more for lower voltages and/or higher V T logic 1% temperature variation 48% voltage variation 51% process variation 4

Gaussian Voltage Variation § Most variation characterization is done with a full Gaussian voltage distribution V DD +10% 3 σ V DD V DD -10% 5

Example IR Drop Allocations 1 power regulator GND board trace board trace 2 ball ball 10 7% package route package route bump bump Global distribution Global distribution 3 9 Mtop to M6 Mtop to M6 M6 M6 M5 M5 4 M4 M4 3% M3 8 M2 M3 strap 5 power gate M2+M1 cell M2+M1 6 7 6

Rectified Voltage Distribution § A more realistic voltage distribution § Needs support from EDA vendors V DD +10% V DD +5% 3 σ Fast domain V DD V DD -5% 3 σ V DD -10% Slow 7

Setup and Hold Margins § Setup and hold times are not really hard boundaries § Statistical constraint characterization is an expensive way to precisely quantify an imprecise value § Need a more efficient and flexible specification Propagation delay Setup and hold are defined by a specified increase in CK->Q Data arrival w.r.t. clock tsu_tp_r th_tp_r 8

Standard Deviations § The number of standard deviations from the mean is N σ § It is often set to 3 σ § It is hard coded into SBOCV tables and statistical hold margins § Sigma based OCV frees users to set N σ for their design § But what is the real yield impact of choosing N σ ? § A design with many critical hold paths may want more than 3 σ § Trying to close timing with conservative margins may hurt overall PPA § What fraction of total yield failures are due to timing marginality? 9

Aging § Today’s critical path is not tomorrow’s critical path § Aging is: § A stochastic process § not deterministic § Workload dependent § Switching activity § Power gating profile § It is not correct to simply re-time with aged models § Need EDA support 10

Cost § The cost to IP providers of creating variation models can be an order of magnitude higher than the cost of providing timing models § Need innovative approaches to modeling variation efficiently § Expect a trade-off between accuracy and cost § Ask about how your IP provider determined the trade-off they applied § Expect a push toward more standardization of § PVT corners § Voltage variation distributions § Temperature variation distributions § Standard deviations 11

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Bio Jim Dodrill received his education at Oklahoma State University and Duke University. During is career he has done custom circuit design and layout, synthesis and place-and-route, full chip assembly, physical and timing verification, internal CAD software development and management. He is currently a Senior Principal Design Engineer in the Advanced Products Division of the Physical Design Group at ARM in Austin, Texas. There he is developing new physical IP and modeling methodology. His current emphasis is on modeling on-chip variation. 13