Lecture 1: Introduction to Digital Logic Design CSE 140: Components - PowerPoint PPT Presentation

Lecture 1: Introduction to Digital Logic Design CSE 140: Components and Design Techniques for Digital Systems Spring 2017 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1

Outlines • Staff – Instructor, TAs, Tutors • Logistics – Websites, Textbooks, Grading Policy • Motivation – Moore’s Law, Internet of Things • Scope – Position among courses – Coverage 2

Information about the Instructor • Instructor: CK Cheng • Education: Ph.D. in EECS UC Berkeley • Industrial Experiences: Engineer of AMD, Mentor Graphics, Bellcore; Consultant for technology companies • Email: ckcheng+140@ucsd.edu • Office: Room 2130 CSE Building • Office hours are posted on the course website – 2-250PM Tu; 330-420PM Th • Websites – http://cseweb.ucsd.edu/~kuan – http://cseweb.ucsd.edu/classes/sp17/cse140-a 3

Information about TAs and Tutors TAs • He, Jennifer Lily email:p3he@ucsd.edu • Jakate, Prateek Ravindra email:pjakate@ucsd.edu • Knapp, Daniel Alan email:dknapp@ucsd.edu • Luo, Mulong email:muluo@ucsd.edu (BSV CSE140L Winter 2017) • Shih, Yishin email:y2shih@ucsd.edu (BSV CSE140L Winter 2017) Tutors • Guan, Yuxiang email:yug049@ucsd.edu • Huh, Sung Rim email:srhuh@ucsd.edu • Li, Xuanang email:xul065@ucsd.edu • Lu, Anthony email:anl176@ucsd.edu • Park, Dong Won email:dwp003@ucsd.edu • Wang, Moyang email:mowang@ucsd.edu • Yao, Bohan email:boyao@ucsd.edu • Yu, Yue email:yuy079@ucsd.edu Office hours will be posted on the course website 4

Logistics: Sites for the Class • Class website – http://cseweb.ucsd.edu/classes/sp17/cse140-a/index.html – Index: Staff Contacts and Office Hrs – Syllabus • Grading policy • Class notes • Assignment: Homework and zyBook Activities • Exercises: Solutions and Rubrics • Forum (Piazza): Online Discussion *make sure you have access • ACMS Labs ieng6: BSV mainly for CSE140L • zyBook: UCSDCSE140ChengSpring2017 • TritonEd: Score record 5

Logistics: Textbooks Required text: • Online Textbook: Digital Design by F. Vahid 1. Sign up at zyBooks.com 2. Enter zyBook code UCSDCSE140ChengSpring2017 3. Fill email address with domain ucsd.edu 4. Fill section A01 or A02 5. Click Subscribe $48 • BSV by Example, R.S. Nikhil and K. Czeck, 2010 (online). Reference texts (recommended and reserved in library) • Digital Design, F. Vahid, 2010 (2 nd Edition). • Digital Design and Computer Architecture, D.M. Harris and S.L. Harris, Morgan Kaufmann, 2015 (ARM Edition). • Digital Systems and Hardware/Firmware Algorithms, Milos D. 6 Ercegovac and Tomas Lang.

Lecture: iCliker for Peer Instruction • I will pose questions. You will – Solo vote: Think for yourself and select answer – Discuss: Analyze problem in teams of three • Practice analyzing, talking about challenging concepts • Reach consensus – Class wide discussion: • Led by YOU (students) – tell us what you talked about in discussion that everyone should know. • Many questions are open, i.e. no exact solutions. – Emphasis is on reasoning and team discussion – No solution will be posted 7

Logistics: Grading Grade on style, completeness and correctness • zyBook exercises: 20% • iClicker: 9% (by participation up to three quarters of classes) • Homework: 15% (grade based on a subset of problems. If more than 85% of class fill out CAPE evaluations, the lowest homework score will be dropped) • Midterm 1: 27% (T 5/2/17) • Midterm 2: 28% (Th 6/8/17) • Final: 1% (take home exam, due 10PM, Th 6/15/17) • Grading: The best of the following – The absolute: A- >90% ; B- >80% of total 100% score – The curve: (A+,A,A-) top 33+ ε % of class; (B+,B,B-) second 33+ ε % 8 – The bottom: C- above 45% of absolute score.

A word on the grading components • zyBook: Interactive learning experience – Reset of answers causes no penalty – No excuse for delay • iClicker: – Clarification of the concepts and team discussion – Participation of three quarters of class – No excuse for missing • Homework: BSV (Bluespec System Verilog) will be used – Practice for exams. Group discussion is encouraged – However, we are required to write them individually for the best results – Discount 10% loss of credit for each day after the deadline but no credit after the solution is posted. – Metric: Posted solutions and rubrics, but not grading results 9

A word on the grading components • Midterms: (Another) Indication of how well we have absorbed the material – Samples will be posted for more practices. – Solution and grading policy will be posted after the exam. – Midterm 2 is not cumulative but requires a good command of the whole class. • Final: – Take home exam – Application of the class materials – Free to use libraries but no group discussion – Fun and educational to work on. 10

BSV: Bluespec System Verilog • High Level Language for Hardware (above Verilog) • Promote modular design methodology • Inventor: Arvind, MIT while he started an Ethernet router chip company. • CSE140L Winter 2017 started BSV (Arvind, Gupta) • CSE140L Spring 2017 adopts BSV (Isaac Chu) • CSE140: Our homework will use BSV (learn by examples) 11

Course Problems…Cheating • What is cheating? –Studying together in groups is not cheating but encouraged –Turned-in work must be completely your own. –Copying someone else’s solution on a HW or exam is cheating –Both “giver” and “receiver” are equally culpable • We have to address the issue once the cheating is reported by TAs or tutors. 12

Motivation • Microelectronic technologies have revolutionized our world: cell phones, internet, rapid advances in medicine, etc. • The semiconductor industry has grown from $21 billion in 1985 to $335 billion in 2015. 13

The Digital Revolution Integrated Circuit: Many digital operations on the same material Vacuum tubes Exponential Growth of Computation (1.6 x 11.1 mm) ENIAC Moore ’ s Law Integrated Circuit Stored Program WWII 1949 1965 Model 14

Building complex circuits Transistor 15

Robert Noyce, 1927 - 1990 • Nicknamed “ Mayor of Silicon Valley ” • Cofounded Fairchild Semiconductor in 1957 • Cofounded Intel in 1968 • Co-invented the integrated circuit 16

Gordon Moore • Cofounded Intel in 1968 with Robert Noyce. • Moore ’ s Law: the number of transistors on a computer chip doubles every 1.5 years (observed in 1965) 17

Technology Trends: Moore’s Law • Since 1975, transistor counts have doubled every two years. 18

Scope • The purpose of this course is that we: – Learn the principles of digital design – Learn to systematically debug increasingly complex designs – Design and build digital systems – Learn what’s under the hood of an electronic component 19

Position among CSE Courses Algos: CSE 100, 101 Application (ex: browser) CSE 140 CSE 120 CSE 131 Operating Compiler System (Mac OSX) Software Assembler Instruction Set Hardware Architecture Processor Memory I/O system CSE 140,141 Datapath & Control Digital Design Circuit Design Transistors • Big idea: Coordination of many levels of abstraction Dan Garcia 

Principle of Abstraction Application programs Software Operating device drivers Systems CSE 30 instructions Architecture registers focus of this course CSE 141 Micro- datapaths architecture controllers adders Logic CSE 140 memories Digital AND gates Circuits NOT gates Analog amplifiers Circuits filters Abstraction: Hiding details when transistors they are not important Devices diodes 21 Physics electrons

Scope: Overall Picture of CS140 Data Path Subsystem Control Subsystem Input Memory File Conditions Pointer Select Sequential Mux machine ALU Control Memory Register CLK: Synchronizing Clock Conditions 22 BSV: Design specification and modular design methodology

Combinational Logic vs Sequential Network x 1 x 1 x 1 . . . . f i (x,s) . . f i (x) f i (x) f i (x) f i (x) s i . . . x n x n x n CLK Sequential Networks Combinational logic: 1. Memory 2. Time Steps (Clock) y i = f i (x 1 ,..,x n ) t = f i (x 1 t ,…,x n t , s 1 t , …,s m t ) y i t+1 = g i (x 1 t ,…,x n t , s 1 t ,…,s m t ) s i 23

Scope Subjects Building Blocks Theory Combinational AND, OR, Boolean Algebra Logic NOT, XOR Sequential AND, OR, Finite State Network NOT, FF Machine Standard Operators, Arithmetics, Modules Universal Logic Interconnects, Memory System Design Data Paths, Methodologies Control Paths 24

Combinational Logic Basics 25

What is a combinational circuit? • No memory • Realizes one or more functions • Inputs and outputs can only have two discrete values • Physical domain (usually, voltages) (Ground 0V, Vdd 1V) • Mathematical domain : Boolean variables (True, False) Differentiate between different representations: • physical circuit • schematic diagram • mathematical expressions 26