Introducing the LSE-PC Pierre Surply Introduction Introducing the LSE-PC Schematics PCB LSE Summer Week 2015 FPGA Code execution Pierre Surply Application Conclusion EPITA 2016 July 18, 2015 Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 1 / 53
Introduction Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 2 / 53
LSE-PC Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 3 / 53
FPGA - CPU Introducing the LSE-PC Pierre Surply VCCA:1 VCCD_PLL:1 VCC1P2:1 C56 C57 C58 +3.3V 100n 100n 100n C48 C49 C50 C51 C52 C53 C54 C55 Introduction 100n 100n 100n 100n 100n 100n 100n 100n VCCA:1 VCCD_PLL:1 VCC1P2:1 +3.3V Schematics +3.3V 35 107 3 75 37 109 1 73 5 29 34 38 45 61 70 78 84 102 116 124 134 138 17 26 40 47 56 62 81 93 117 122 130 139 VCCA1 VCCA2 VCCA3 VCCA4 VCCD_PLL1 VCCD_PLL2 VCCD_PLL3 VCCD_PLL4 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO7 VCCIO8 VCCIO8 10k 10k R90 R91 PCB 21 nCE IO 7 LED_TST 9 10 nSTATUS EP4CE22E22C7N IO BHE 14 FPGA1 11 +5V nCONFIG IO A1 +5V FPGA_CLK 23 28 CLK1 IO 8 9 10 21 32 39 42 48 57 69 71 84 91 97 24 CLK2 IO 30 BLE CPU_CLK 25 31 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc C59 C60 C61 C62 ADS CLK3 IO READY FPGA 91 32 CLK4 IO HOLD 90 33 15 18 A1 100n 100n 100n 100n CLK5 IO HLDA CLK2 A1 A2 89 80386SXLP 51 CLK6 D0 D0 A2 A3 88 CLK7 IO 39 1 D0 A3 52 126 42 D1 D1 100 CPU1 53 A4 CLK8 IO D1 A4 127 43 D2 D2 99 54 A5 CLK9 IO/PLL1_CLKOUTp D2 A5 128 44 D3 D3 96 55 A6 CLK10 IO/PLL1_CLKOUTn D4 D4 D3 A6 A7 Code 129 46 95 56 CLK11 IO D5 D5 D4 A7 A8 55 CLK12 IO 49 94 D5 A8 58 54 50 D6 D6 93 59 A9 +3.3V CLK13 IO D6 A9 53 51 D7 D7 92 60 A10 CLK14 IO D7 A10 execution 52 D8 90 61 A11 CLK15 D8 D9 D8 A11 A12 10k 58 89 62 IO D9 D10 D9 A12 A13 86 IO/DEV_OE IO 59 +5V 88 D10 A13 64 R92 87 60 D10 D11 87 65 A14 IO/DEV_CLRn IO D11 A14 92 64 D11 D12 86 66 A15 CONF_DONE IO 20k D12 A15 98 65 D12 D13 83 70 A16 IO/INIT_DONE IO D13 D14 D13 A16 A17 99 IO/CRC_ERROR 66 R83 82 72 Application RAMWE IO D14 D15 D14 A17 A18 RAMCS 103 IO/CLKUSR IO 67 81 D15 A18 73 68 D15 74 A19 IO A19 101 69 A23 16 75 A20 NC IO/nCEO IO ADS ADS A20 94 71 A22 6 76 A21 MSEL0 MSEL0 IO/PLL4_CLKOUTp A21 NA A21 A22 96 IO/PLL4_CLKOUTn 72 7 79 MSEL1 MSEL1 READY READY A22 A23 MSEL2 97 MSEL2 A23 80 13 76 A20 4 19 DATA0 IO/DATA0 IO HOLD HOLD BHE BHE +5V Conclusion 12 77 A19 3 17 DCLK DCLK IO HLDA HLDA BLE BLE 8 80 A18 nCSO FLASH_nCE/nCSO IO A17 6 83 40 25 ASDO IO/DATA1/ASDO IO A16 INTR INTR W/R WR IO 85 NMI 38 NMI D/C 24 DC R21 20k 15 33 23 TDI TDI RESET RESET M/IO MIO 20 100 A15 28 26 TDO TDO IO FLT FLT LOCK LOCK 16 104 A14 TCK TCK IO A13 18 105 37 TMS TMS IO A12 PEREQ PEREQ IO 106 BUSY 34 BUSY 36 ERROR ERROR 110 A11 IO Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss 111 A10 IO A9 IO/PLL2_CLKOUTn 112 A8 2 5 11 12 13 14 22 35 41 49 50 63 67 68 77 78 85 98 IO/PLL2_CLKOUTp 113 114 A7 IO 115 A6 IO 119 A5 IO 120 A4 IO A3 IO 121 125 A2 IO 132 IO/DATA2 INTR 133 IO/DATA3 NMI IO 135 RESET 136 IO LOCK 137 IO/DATA5 UART_TX 141 IO UART_RX 142 IO WR IO/PLL3_CLKOUTn 143 DC IO/PLL3_CLKOUTp 144 MIO GNDA1 GNDA2 GNDA3 GNDA4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 36 108 2 74 19 27 41 48 57 63 82 95 118 123 131 140 4 22 79 Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 4 / 53
CPU Introducing the LSE-PC Pierre Surply +5V +5V 8 9 10 21 32 39 42 48 57 69 71 84 91 97 CPU_CLK Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc C59 C60 C61 C62 Introduction A1 15 18 100n 100n 100n 100n CLK2 A1 A2 80386SXLP 51 A2 D0 A3 1 52 Schematics D0 A3 CPU1 D1 100 53 A4 D1 A4 D2 A5 99 54 D2 A5 D3 A6 96 55 D3 A6 D4 A7 95 56 PCB D4 A7 D5 94 58 A8 D5 A8 D6 A9 93 59 D6 A9 D7 A10 92 60 D7 A10 D8 A11 FPGA 90 61 D8 A11 D9 89 62 A12 D9 A12 D10 A13 +5V 88 64 D10 A13 D11 A14 87 65 D11 A14 D12 A15 Code 86 66 D12 A15 20k D13 83 70 A16 D13 A16 D14 A17 execution R83 82 72 D14 A17 D15 A18 81 73 D15 A18 A19 74 A19 16 75 A20 ADS ADS A20 Application A21 6 76 NA A21 A22 7 79 READY READY A22 A23 80 A23 4 19 HOLD HOLD BHE BHE +5V Conclusion 3 17 HLDA HLDA BLE BLE 40 25 INTR INTR W/R WR 38 24 20k NMI NMI D/C DC 33 23 RESET RESET M/IO MIO 28 26 FLT FLT LOCK LOCK 37 PEREQ PEREQ 34 BUSY BUSY 36 ERROR ERROR Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss 2 5 11 12 13 14 22 35 41 49 50 63 67 68 77 78 85 98 NG80386SXLP20 : 20MHz 386 SX from 1986 Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 5 / 53
FPGA Introducing the LSE-PC Pierre Surply VCCA:1 VCCD_PLL:1 VCC1P2:1 +3.3V Introduction +3.3V 35 107 3 75 37 109 1 73 5 29 34 38 45 61 70 78 84 102 116 124 134 138 17 26 40 47 56 62 81 93 117 122 130 139 VCCA1 VCCA2 VCCA3 VCCA4 VCCD_PLL1 VCCD_PLL2 VCCD_PLL3 VCCD_PLL4 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO7 VCCIO8 VCCIO8 10k 10k R90 R91 Schematics 21 7 nCE IO LED_TST 9 EP4CE22E22C7N 10 nSTATUS IO BHE 14 FPGA1 11 nCONFIG IO 23 28 A1 FPGA_CLK CLK1 IO 24 30 CLK2 IO BLE PCB 25 31 ADS CLK3 IO READY 91 32 CLK4 IO HOLD 90 33 CLK5 IO HLDA 89 CLK6 Altera Cyclone IV 88 39 D0 CLK7 IO D1 126 CLK8 IO 42 FPGA D2 127 CLK9 IO/PLL1_CLKOUTp 43 D3 128 IO/PLL1_CLKOUTn 44 CLK10 D4 129 46 CLK11 IO D5 55 49 CLK12 IO D6 54 50 +3.3V CLK13 IO D7 53 51 CLK14 IO EP4CE22E22C7N Code 52 CLK15 10k 58 D8 IO 86 59 D9 R92 IO/DEV_OE IO 87 60 D10 execution IO/DEV_CLRn IO 92 64 D11 CONF_DONE IO 98 65 D12 IO/INIT_DONE IO 99 66 D13 RAMWE IO/CRC_ERROR IO 103 67 D14 RAMCS IO/CLKUSR IO EQFP 144 pins 68 D15 IO 101 69 A23 Application NC IO/nCEO IO 94 71 A22 MSEL0 MSEL0 IO/PLL4_CLKOUTp 96 72 A21 MSEL1 MSEL1 IO/PLL4_CLKOUTn 97 MSEL2 MSEL2 A20 DATA0 13 IO/DATA0 IO 76 A19 DCLK 12 DCLK IO 77 A18 nCSO 8 FLASH_nCE/nCSO IO 80 Conclusion A17 22320 logic elements 6 IO/DATA1/ASDO 83 ASDO IO A16 85 IO 15 TDI TDI A15 20 100 TDO TDO IO A14 16 104 TCK TCK IO A13 18 105 TMS TMS IO 106 A12 IO Released in 2009 110 A11 IO 111 A10 IO 112 A9 IO/PLL2_CLKOUTn 113 A8 IO/PLL2_CLKOUTp 114 A7 IO 115 A6 IO 119 A5 IO 120 A4 IO 121 A3 IO 125 A2 IO IO/DATA2 132 INTR IO/DATA3 133 NMI 135 IO RESET 136 IO LOCK 137 UART_TX IO/DATA5 141 UART_RX IO 142 IO WR 143 IO/PLL3_CLKOUTn DC 144 GNDA1 GNDA2 GNDA3 GNDA4 IO/PLL3_CLKOUTp MIO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 36 108 2 74 19 27 41 48 57 63 82 95 118 123 131 140 4 22 79 Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 6 / 53
5V Device Compatibility Introducing the LSE-PC Pierre Surply LOGIC DIAGRAM (POSITIVE LOGIC) DGG OR DGV PACKAGE (TOP VIEW) Introduction 2 46 NC 1OE 1 48 1A1 SW 1B1 1A1 2 47 2OE Schematics 1A2 3 46 1B1 1A3 1B2 4 45 PCB 1A4 1B3 5 44 12 36 1A5 6 43 1B4 1A10 SW 1B10 FPGA 1A6 1B5 7 42 GND GND 8 41 Code 1A7 9 40 1B6 48 1B7 execution 1A8 10 39 1OE 1A9 1B8 11 38 1A10 12 37 1B9 Application 1B10 2A1 13 36 2A2 2B1 14 35 Conclusion 13 35 V CC 15 34 2B2 2A1 SW 2B1 2A3 16 33 2B3 GND GND 17 32 2A4 2B4 18 31 2A5 19 30 2B5 24 25 2B6 2A6 20 29 2A10 SW 2B10 2A7 2B7 21 28 2A8 22 27 2B8 2B9 2A9 23 26 47 2A10 2B10 24 25 2OE NC - No internal connection Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 7 / 53
5V Device Compatibility Introducing the LSE-PC Pierre Surply Introduction Schematics R 1 = V CC PCB Cyclone Device I OH 5.0-V Device FPGA 3.0 - 3.4 V ± 0.25 V 5.0 V ± 0.25 V V CCIO V IN = V CCIO + 0 . 7 V Code V CC V CCIO execution PCI Clamp R 2 = ( V CC − V IN ) − ( R 1 × I OH ) Application I I R 2 I OH Conclusion Model as R 1 B R 2 = 120Ω Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 8 / 53
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