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Incremental Layer Assignment for Critical Path Timing Derong Liu 1 , - PowerPoint PPT Presentation

Incremental Layer Assignment for Critical Path Timing Derong Liu 1 , Bei Yu 2 , Salim Chowdhury 3 , and David Z. Pan 1 1 ECE Department, University of Texas at Austin, Austin, TX, USA 2 CSE Department, Chinese University of Hong Kong, Hong Kong 3


  1. Incremental Layer Assignment for Critical Path Timing Derong Liu 1 , Bei Yu 2 , Salim Chowdhury 3 , and David Z. Pan 1 1 ECE Department, University of Texas at Austin, Austin, TX, USA 2 CSE Department, Chinese University of Hong Kong, Hong Kong 3 Oracle Corp., Austin, TX, USA 1

  2. Introduction t As VLSI technology scales to deep submicron › Interconnect dominates timing issues › Global routing – integral part of timing convergence flow 2D Global Routing Layer Assignment 3D Global Routing Global Routing Flow 2

  3. Previous Works on GR and LA t Example papers on global routing and layer assignment: › Timing-driven GR [Liu et al. TCAD’13] › Via count and overflow minimization during layer assignment - NVM [Liu+, ASPDAC’11] › Delay-driven layer assignment [Yu+, ICCAD’15] t Limitations of previous layer assignment: › Net-by-net method may lead to sub-optimal results › Focus on sum of net delays › Lack global optimization › Linear approximation of via delays influences accuracy. 3

  4. Contributions of this Work t A novel incremental layer assignment framework for critical path timing with via delays t Semidefinite programming (SDP) modeling for better optimal solutions t Self-adaptive partitioning methodology based on K*K partitions for speed-up 4

  5. Problem Formulation t Critical Path Layer Assignment (CPLA) › Given a 3-D grid graph, edge and layer information, initial layer assignment solution and set of critical nets › Minimize: critical path timing (Elmore delay) › Subject to: edge capacity constraints Non-Critical Nets: n1 n2 ; Critical Net: n3 n3 n2 n1 n2 n1 n3 (a) (b) 5

  6. CPLA Algorithm t Mathematical Formulation Segment costs Via costs t Constraints: › Each segment should be assigned on one and only one layer › Edge capacity constraint: › Via capacity constraint: 6

  7. Self-adaptive Quadruple Partition t K x K division [Yu+, ICCAD’15] › Unbalanced computation overhead t Limit the number of segments in each partition › Each thread deals with workload in a well-balanced manner 7

  8. Semidefinite Programming t Input: parameter matrix T t Output: variable matrix X Segment costs Via costs 8

  9. Example t Segments S1 and S2 t 4 layers: › Layer 1 and 3 for x-dimension › Layer 2 and 4 for y-dimension S1 S1 S1 S1 T(M1): 35.2 T(M3): 15.6 � � � � � � � � T(M2): 47.8 T(M4): 23.9 S2 S2 S2 S2 � � � � � � � � t Post mapping strategy provides integer solutions 9

  10. Experimental Results t Implemented the framework in C++ t ILP solver -- GUROBI t SDP solver – CSDP t Parallel implementation – OpenMP t Evaluation on ISPD’08 global routing benchmarks t Performance Metrics › Average Critical Path Timing › Worst Critical Path Timing › # of Via capacity violation › # of Via 10

  11. Evaluation on ISPD’08 Benchmarks t Initial global routing input: › Generated by NCTU-GR 2.0 [Liu et al. TCAD’13] t Initial layer assignment: › From NVM [Liu et al. ASPDAC’11] › Targeting via number and overflow minimization t Wire resistance and capacitance values obtained from industry settings t Release 0.5% critical and non-critical nets t Compared with TILA [Yu et al. ICCAD’15] 11

  12. Delay Comparison Results t ISPD’08 Global Routing Benchmarks › 14% improvement in Avg(T cp ) › 4% improvement in Max(T cp ) 12

  13. Via Comparison Results t ISPD’08 Global Routing Benchmarks › Via Overflow (#OV) decreases by 10% › Similar number of vias 13

  14. Conclusion t Propose Incremental Layer Assignment for Critical Path Timing ( CPLA ) algorithm › Self-adaptive partition provides balanced workload for multiple threads and potential speed-up › Semidefinite programming (SDP) relaxation › Post mapping satisfies constraints t CPLA suitable for future heterogeneous layer structures 14

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  16. Overview t Introduction t Problem Formulation t Algorithms t Experimental Results t Conclusion 16

  17. Model Description t Elmore timing model: › Consider both segment delay and via delay s4 s3 Maximum Path Delay: Sink t(s1) + t(s2) + t(s3) + t(s4) + t(v1) v1 s1 s2 17

  18. Partition Size Impact t Different number of segments in each partition Impact on Avg ( T cp ); Impact on Max ( T cp ); Impact on runtime 18

  19. Mapping Algorithm t Provide integer solutions › For each edge with critical nets: Find the current highest layer j to assign segments cap(j) = allowable number of segments to assign Select cap(j) segments with highest solutions Assign these segments on layer j of edge N Finish all layers? Y Exit 19

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