TILA: Timing-Driven Incremental Layer Assignment Bei Yu 1,2 , Derong Liu 1 , Salim Chowdhury 3 , and David Z. Pan 1 1 ECE Department, University of Texas at Austin, Austin, TX , USA 2 CSE Department, Chinese University of Hong Kong 3 Oracle Corp., Austin, TX, USA 1
Overview t Introduction t Problem Formulation t Algorithms t Experimental Results t Conclusion 2
Introduction t VLSI technology scales to deep submicron › Interconnect delay t Interconnect synthesis › Timing-driven routing › Global routing -- part of a timing convergence flow Global Routing Flow 3D Global Routing 2D Global Routing Layer Assignment 3
Introduction t Layer assignment: › Assign segments to metal layers › Impossible to assign all segments on higher layers Wire Via Top Metal Layers Intermediate Metal Layers Lower Metal Layers Metal 1 4
Previous Works on GR and LA t Many papers on global routing and layer assignment, e.g. › Routability-driven GR [Cho+, TCAD’07] Global Routing › Timing-driven GR [Liu et al. TCAD’13] › Via count and overflow minimization during Timing Optimization layer assignment - NVM [Liu+, ASPDAC’11] (Buffering) › Delay-driven layer assignment [Ao+, Layer Assignment ISPD’13] t Limitations of previous layer assignment: Detailed Routing › Most focus on via minimization › Via delays are often ignored Post-Routing Optimization › Net-by-net method may lead to local optimality 5
Contributions of this Work t The first timing-driven incremental layer assignment (TILA) that integrates via delay t Solve multiple nets simultaneously t Incremental approach to provide fast turn-around-time t Lagrangian relaxation based optimization to improve total wire and via delay via min-cost flow iteratively t Multi-processing of K * K partitions for speed-up t Effectiveness demonstrated by ISPD’08 and industry benchmarks 6
Model Description t Timing model: › Elmore Delay ( C down , R ) › Consider both segment delay and via delay Sink Driver Via Delay 7
Problem Formulation t Timing-driven Incremental Layer Assignment (TILA) › Given initial layer assignment solution and critical ratio α ¡ › Minimize: sum of segment and via delays of selected nets › Subject to: via capacity and edge capacity constraints Non-Critical Nets: n1 n2 ; Critical Net: n3 n3 n2 n1 n2 n1 n3 One Example 8
TILA Algorithm t Mathematical Formulation Via Delay Segment Delay t Constraints: › Each segment should be assigned on one and only one layer › Edge capacity constraint: › Via capacity constraint: 9
TILA Algorithm t Lagrangian Relaxation Subproblem (LRS) Integrate via capacity constraint with Lagrangian Multipliers (LMs) › Solve the LRS iteratively t Linearize the quadratic term approximately: › Based on the values in previous iteration t Solve the LRS through a min-cost network flow model t Satisfy the edge capacity constraint t Guarantee one segment on one layer 10
TILA Algorithms t Min-cost Flow Model › Inherent uni-modular property to ensure integer solutions › Directed Graph G (V,E) Layer Vertices Segment Vertices Pseudo Start Vertex Pseudo End Vertex Capacity : 1 Cost : 0 Capacity: edge capacity Cost : 0 Capacity : 1 Cost : assigning penalty 11
TILA Algorithm t Algorithm Flow Critical Ratio α Select nets with α Initial Layer Assignment Solution Initialize C down and LMs Improvement < Specified Ratio converge? End Or Iteration number > MaxIter Y N Solve LRS Min-cost flow model Update C down and LMs 12
Incremental Approach t Critical & Non-critical Net Selection › Most Critical nets: improve the timing › Most non-critical nets: release more high layers resources Calculate Net Delay Select α%# nets with Most critical nets selection worst delay Select # nets based on Most non-critical nets selection delay and sharing edges Re-assign selected nets Nets Selection Flow 13
Speed-up Techniques t Parallel Scheme › Divide grid model into K x K partitions › Recent results by peer threads can be considered 4 * 4 partitions 14
Experimental Results t Implemented the framework in C++ t Tested on Linux machine with eight 3.3GHz CPUs t Min-cost flow solver › LEMON open source graph library t Parallel computation with OpenMP › Default thread number as 6 and K set as 6 t Evaluation on both academia and industrial benchmarks t Performance Metrics › Average Delay › Maximum Delay › Via capacity violation# › Via# 15
Evaluation on ISPD’08 Benchmarks t Initial global routing input: › Generated by NCTU-GR 2.0 [Liu et al. TCAD’13] t Initial layer assignment: › From NVM [Liu et al. ASPDAC’11] › Targeting via number and overflow minimization t Wire resistance and capacitance values obtained from [Hsu et al. ICCAD’14] t Via resistance and capacitance normalized from industry t Release 1% and 5% critical and non-critical nets 16
Delay Comparison Results t ISPD’ 0 8 Global Routing Benchmarks t TILA-1%: › 53% improvement by D max and 10% improvement by D avg t TILA-5%: › 53% improvement by D max and 18% improvement by D avg 17
Via Comparison Results t ISPD’ 0 8 Global Routing benchmarks t TILA-1% › OV# decreases by 7% and Via# increases by 3% t TILA-5% › OV# decreases by 11% and Via# increases by 12% 18
Experimental Results t Impact of different critical / non-critical ratio › Releasing 1% is enough for maximum delay › Trade-off between average delay and speed D max : max delay; D avg : average delay; run time 19
Industrial Benchmarks Results t Industry tool to generate initial routing solution t Use industry resistance and capacitance OV #: overflow number; D avg : average delay; D max : max delay; via #: total via number 20
Conclusion t We proposed a new Timing-driven Incremental Layer Assignment (TILA) algorithm › Select a subset of critical and non-critical nets › Lagrangian relaxation based global optimization › Min-cost network flow to solve iteratively › Multi-threading t TILA can work smoothly with any global router and adapt easily to future heterogeneous layer structures t New research needed to shed light on “classical” EDA problems 21
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