IEE5008 Autumn 2012 Memory Systems Quad Data Rate SRAM for the - PowerPoint PPT Presentation

IEE5008 –Autumn 2012 Memory Systems Quad Data Rate SRAM for the High-Throughput Communication Systems Nina Mitiukhina Electrical Engineering and Computer Science International Graduate Program National Chiao Tung University ninusyamit@gmail.com Chih-Yuan, Chang 2012 Nina Mitiukhina 2012

Outline  Introduction  Functional Description  Controller Function  System-Level Issues  Impact of the Device Scaling on System Performance  Applications  Conclusion  Reference Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 2

Introduction QDR SRAMs are a family of SRAMs with separate Inputs and Outputs that each operate at Double Data Rates. Demand is growing rapidly for memories optimized for high bandwidth . The relentlessly expanding amount of information that travels over the Internet is creating the need for more and faster systems capable of routing and switching data across the globe. Higher-bandwidth memory is a requirement for these systems, and the QDR standard is specifically designed to address this need. Devices are designed to greatly increase memory bandwidth compared to existing SRAM solutions in applications such as switches and routers, and will typically be used for look-up tables, linked lists and controller buffer memory. To the right  SRAM Memory suited for networking architecture performance comparison. QDR SRAM devices are compared against other SRAM families such as double data rate (DDR), zero-bus turnaround (ZBT), and SyncBurst. Compasiron assumes 125 MHz clock speed. Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 3

Introduction  QDR Evolution Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 4

Introduction  QDR Consortium. Milestones. In 1999, the QDR SRAM Co-Development Team was created to define a new family of SRAM architectures for high-performance communications applications. Participating companies work closely together to ensure multiple sources for the new QDR SRAMs by developing pin- and function-compatible products. 1999 – 1) QDR-I specifications released; 2) Cypress, IDT and Micron team to provide new QDR SRAM architecture. 2001 – 1) JEDEC approves QDR-I; 2) QDR-I 9Mb sampled; 3) NEC, Samsung, Hitachi joins QRD consortium 4) QDR-ll specifications released 5) QDR-ll 18Mb sampled 2002 - 1) JEDEC approves QDR-II family of high-speed SRAM products 2) NEC Electronics ships QDR-II DDR-II family of high-speed SRAM products 3) Samsung leads next-generation networking with industry's first 36Mb QDR-ll SRAM 2006 - 1) QDR-ll+ and DDR-l SRAM specifications released 2) ODT(On Die Termination) feature made available in QDR-II+ products 3) QDR-II+ maximum frequency increased to 550MHz 2011 - QDR-ll+ Xtreme specifications released Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 5

Introduction  QDR Product Family Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 6

Functional Description  QDR SRAM distinctive features: 1) Separate write data (D) and read data (Q) ports that support simultaneous reads and writes and allow back-to-back transactions without the contention issues that can occur when using a single bidirectional data bus. 2) A shared address bus that alternately carries the read and write addresses. 3) A memory core made up of multiple SRAM arrays, permitting double data rate (DDR) access and a transfer rate of up to four words on every cycle. Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 7

Functional Description  Example: burst-of-2 architecture Signal Signal Name Description Type Clock K, Kn Clock inputs to QDR SRAM. output K_FB_OUT Is fed back to the controller as K_FB_IN to imitate the data flight times to and from QDR SRAM device. Clock K_FB_IN Used by controller to generate input READ_CLK for clocking in data. RPSn Active-low read port select Control signal, sampled on the rising output edge of K. WPSn Active-low write port select signal, sampled on the rising edge of K. BWSn[1..0] Active-low byte write select signal, sampled on the rising edge of K. Addres A[17..0] QDR SRAM’s address signals. s Address inputs are sampled on output the rising edge of K for reads and on the rising edge of Kn for writes. Data D[17..0] Read data output from QDR input SRAM. Data Q[17..0] Write data input to the QDR output SRAM. Table 1. QDR SRAM Device Interface Signals Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 8

Functional Description  Present Interface Signals Clock Signals Two pairs of clocks: K and Kn, and C and Cn. In dual-clock mode, K/Kn clocks are used for write accesses and the C/Cn clocks for read accesses. Device can also be set to the single- clock mode, where the K and Kn clocks are used for both reads and writes (C/Cn tied to VDD). Control Signals QDR SRAM devices use two control signals, write port select (WPSn) and read port select (RPSn), to control write and read operations, respectively. A third control signal, byte write select (BWSn), writes only one byte of data at a time, if necessary. Address Signals QDR SRAM devices use one address bus (A) for both read and write addresses. Data Signals QDR SRAM devices use two unidirectional data buses, one for writes (D) and one for reads (Q). Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 9

Functional Description  QDR SRAM Functionality QDR SRAM devices have a two-word or four-word burst capability. “Burst” : number of data words that are read or written on a single access. Burst-of-2 operation supports two-word data transfer on all write and read transactions. Requires a relatively simple controller implementation. Burst-of-4 supports four-word data transfers on all write and read; address bus activity is reduced, more complicated interfacing with controller circuitry is needed. Note on Read/Write cycle: Independent read and write data paths, along with the cycle-shared address bus, allow read and write operations to occur in the same clock cycle. Performing concurrent reads and writes does not change the functionality of either transaction. If a read request occurs simultaneously with a write request at the same address, the data on D is forwarded to Q; therefore, latency is not required to access valid data. Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 10

Functional Description  Burst-of-2 Timing Diagram Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 11

Functional Description  Burst-of-4 Timing Diagram Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 12

Controller Function  Example: Altera APEX 20KE Table 1. QDR SRAM Device Interface Signals Signal Signal Name Description Type Clock K, Kn Clock inputs to QDR SRAM. output K_FB_OUT Is fed back to the controller as K_FB_IN to imitate the data flight times to and from QDR SRAM device. Clock K_FB_IN Used by controller to generate input READ_CLK for clocking in data. RPSn Active-low read port select Control signal, sampled on the rising output edge of K. WPSn Active-low write port select signal, sampled on the rising edge of K. BWSn[1..0] Active-low byte write select signal, sampled on the rising edge of K. Addres A[17..0] QDR SRAM’s address signals. s Address inputs are sampled on output the rising edge of K for reads and on the rising edge of Kn for writes. Data D[17..0] Read data output from QDR input SRAM. Data Q[17..0] Write data input to the QDR output SRAM. Note: Controller read and write data path are independent thus it can perform reads and writes Table 2. Example of the User Interface Signals together or separately. Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 13

Controller Function  Write cycle waveform (burst-of-2) Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 14

Controller Function  Read cycle waveform (burst-of-2) Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 15

System-Level Issues  High-Speed Transceiver Logic I/O Pins (HSTL I/O) Circuit board layout affects signal integrity. Transmission line effects will affect signals even on short trace runs at the high speeds. Trace length and geometry are critical to maintaining signal integrity and ensuring an error free system operation. To control reflections, the impedance of integrated circuit output pad drivers must be matched to the impedance of the transmission lines to which the pads are connected. HSTL (high-speed transceiver logic) controlled impedance I/O pads use an on-chip impedance matching network that compensates for PVT variations. The QDR SRAM device interface requires the use o the HSTL I/O standard. Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 16

System-Level Issues  Clock Generation 1) INCLK – Input clock; 2) WRITE_CLK and WRITE_CLK_90 – controller clocks 1) K and Kn – QDR SRAM clocks 2) K_FB_IN and K_FB_OUT – Controller feedback clock 1) READ_CLK – Read data capture clock. Note: All L1 traces should be of equal length, all L2 traces should be of equal length as well. Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 17

System-Level Issues  Timing: Write Cycle Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 18

System-Level Issues  Timing: Read Cycle Nina Mitiukhina 2012 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012 19