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The New Standard / SigmaDDR-IIIe SigmaQuad-IIIe Quad Data Rate, - PowerPoint PPT Presentation

High Transaction Rate Memories: The New Standard / SigmaDDR-IIIe SigmaQuad-IIIe Quad Data Rate, B2 at 675 MHz GS8673 1.35 GHz Transaction Rate 72Mbit ECCRAM 1.35 Gb/s per pin data 97 Gb/s per part bandwidth Quad


  1. High Transaction Rate Memories: The New Standard

  2. ™ / SigmaDDR-IIIe ™ SigmaQuad-IIIe • Quad Data Rate, B2 at 675 MHz GS8673 • 1.35 GHz Transaction Rate 72Mbit ECCRAM • 1.35 Gb/s per pin data • 97 Gb/s per part bandwidth • Quad Data Rate, B4 at 675 MHz • 1.35 Gb/s per pin data • 97 Gb/s per part bandwidth • Double Data Rate, B2 at 675 MHz • 1.35 Gb/s per pin data • 48 Gb/s per part bandwidth • On-Chip ECC: virtually zero SER 260 ball, 1 mm pitch BGA 2

  3. Development Strategy Part 1: Keep What Works • BGA Package with 1 mm Pad Pitch • No special assembly requirements • Conventional Control Truth Table • Familiar Read and Write protocols • Echo Clocks and Output Valid Signals • DLL-controlled Output Data timing • Programmable Output Driver Impedance • ZQ control of Output impedance 3

  4. Development Strategy Part 2: Fix What Doesn’t • Better Signal Integrity • Larger Output Data Valid Window • New High Performance Pinout • User-programmable ODT (On-Die Input Termination) • Programmable value • Selectable input pin coverage • KD & KD# Data Input Clocks • Lower Signaling and Core Power Consumption • 1.3 V V DD • 1.2 V JEDEC BIC thru 1.5 V JEDEC HSTL I/O 4

  5. Higher Performance Pinouts SigmaQuad/DDR: IIIe SigmaQuad/DDR: I, II, II+ 165 BGA : 11 x 15 Array, 15 x 17 mm, 1 mm pitch 260 BGA: 13 x 20 Array, 14 x 22 mm, 1 mm pitch 5

  6. Improved Data Valid Windows ~760ps ~780ps Modern 260 BGA @ 500 MHz 165 BGA @ 333 MHz 40ohm driver; 60ohm thevenin termination 40ohm driver; 60ohm thevenin termination 1.0 GHz data rate ; 1.2 V output voltage 666 MHz data rate ; 1.5 V output voltage Result: ~760ps eye @ 1000ps Tcycle Result: ~780ps eye @ 1500ps Tcycle 76% data valid window 52% data valid window 6

  7. Type-IIIe SRAMs - Ordering Options Read Latency Product Option: Speed Bins (MHz) (cycles) Quad Data Rate 2, 3 500 550 625 675 Burst of 2 Quad Data Rate 2, 3 500 550 625 675 Burst of 4 Double Data Rate 2, 3 500 550 625 675 Burst of 2 7

  8. Type-IIIe SRAMs are Qualified and Shipping in Volume Questions? IIIeinfo@gsitechnology.com 8

  9. Thank You.

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