Hammer VLSI Flow John Wright UC Berkeley johnwright@berkeley.edu - PowerPoint PPT Presentation

Hammer VLSI Flow John Wright UC Berkeley johnwright@berkeley.edu

Tutorial Roadmap Custom SoC Configuration FireMarshal RTL Generators Bare-metal & RISC-V Multi-level Custom Accelerators Peripherals Linux Cores Caches Verilog Custom Workload RTL Build Process FIRRTL FIRRTL IR Verilog QEMU & Spike Transforms Software RTL Simulation FireSim FPGA-Accelerated Simulation Automated VLSI Flow Tech- Tool- VCS Verilator Simulation Debugging Networking Hammer plugins plugins

Agenda • VLSI flow • Challenges in VLSI flows • Hammer physical design flow principles • How to use Hammer • Demo SHA3 accelerator physical design flow 3

VLSI for Real Hardware Remember this slide from the introduction? Real hardware requires VLSI work! 4

An “Advertised” VLSI Flow T T C C L L s s c c r r i i p p t t Place- Logic Synthesis and- Chip Verilog Logic Gates Design Route s s l e l e l u C R d g r a n d i t n u a o t R S 5

An “Advertised” VLSI Flow T T C C L L s s c c r r i i p p t t Place- Logic Synthesis and- Chip Verilog Logic Gates Design Route s s l e l e l u C R d g r a n d i t n u a o t R S 6

A Real VLSI Flow Unzip PDK; Slowly discover there are Foundry delivers PDK Send a few emails to RTL is ready Download a new PDK tarball the foundry missing CAD-tool- specific files Find out you are Power strap spec using the wrong time Finally start place- Iterate on synthesis doesn't meet DRC, Try running synthesis and-route for a week units and standard causes LVS problems cell library Fix power straps; Fix DRC problems; Spend a while fixing a Switch to a new Discover some continue with place- timing path in the Fix timing paths; tape foundry and CAD standard cells have and-route; discover RTL, while noting out a chip vendor; throw all this DRC problems when the design misses what went wrong with work away abutted timing the tool 7

A Real VLSI Flow • The physical design (VLSI) flow must be rebuilt for each project • Overhead compounded by • Changing CAD tool vendors Tool • Commands change. Features work/ don’t work Concerns • File formats / library locations • Using a new process technology Process Technology • SRAMs (compiled/pre-generated?) Concerns • New DRC rules • Changing the design itself Design • Floorplanning / power / clock Concerns 8

Why So Complicated? • Designs are getting bigger and more complex Tool Concerns • EDA industry evolution Design Concerns • EDA tools evolve bottom-up through patches and Process acquisitions Technology Concerns • No [real] common exchange formats or APIs • All physical design concerns mixed together Magic TCL Script 9

Why So Complicated? • Designs are getting bigger and more complex Tool Concerns • EDA industry evolution Design Concerns • EDA tools evolve bottom-up through patches and Process acquisitions Technology Concerns • No [real] common exchange formats or APIs • All physical design concerns mixed together Magic TCL Script 10

Hierarchical Design • Why hierarchical physical design? • Modern chips are complex w/ prohibitively large place-and-route time Top • Divide-and-conquer alleviates this problem A A • Problem: Hierarchical isn’t “Free” • Floorplanning is complicated • Alignment of power straps, placement sites, and pins AA AA C • Tools want physical and logical hierarchies to match • How to determine logical hierarchy? AA AA • Constraining timing on the I/O boundaries • Hammer helps simplify hierarchical flows 11

Why So Complicated? • Designs are getting bigger and more complex Tool Concerns • EDA industry evolution Design Concerns • EDA tools evolve bottom-up through patches and Process acquisitions Technology Concerns • No [real] common exchange formats or APIs • All physical design concerns mixed together Magic TCL Script 12

Some TCL code… • Consider a hypothetical power strap creation command: set some_proprietary_option M1 set some_other_proprietary_option M3 create_power_stripes -nets {VSS VDD} –layer M2 –direction vertical \ -via_start M1 –via_stop M3 –group_pitch 43.200 -spacing 0.216 -width 0.936 \ -area [get_bbox -of ModuleABC] \ -start [expr [lindex [lindex [get_bbox –of ModuleABC] 0] 0] + 1.234] # Repeat for each layer! • Writing a line of TCL to place power straps contains: • The command itself and its options (tool-specific) • DRC-clean spacing, width, and direction information (technology-specific) • Group pitch, domain, floorplan information (design-specific) 13 *Fake commands inspired by real commands due to EULA

Hammer “Separation of Concerns” • Solution: Add a layer of abstraction Design: Tool: Floorplan In/out files • • • Three categories of flow input Clocks TCL code • • • Design-specific Hierarchy Tech. file • • • Tool/Vendor-specific formats • Technology-specific • Hammer Goal: specify all three Tech.: separately • Allow reusability SRAMs • • Allow for multiple “small” experts instead Std. cells • of a single “super” expert Stack-up • • Build abstractions/APIs on top Power straps • 14

Design Concerns Separated • Floorplan Concerns • Physical hierarchy • Placement constraints Design Tool • Pin constraints Tech. • Clock constraints: frequencies, pin delays, etc. • Design modifications: retiming, scan insertion, etc. • Solution: Store these in an Intermediate Representation (IR) • Emit from high-level input source • Consume by hammer to produce TCL commands and perform quality checks • Need tool plugins to know what TCL to write! 15

Tool Concerns • Site-level problems Separated Concerns • Installation path, license servers, tool versions • Allow these to be overridden by configuration files Design Tool • TCL command interface Tech. • Not standardized between vendors! • No commitment to preserve API across versions! • Solution: Implement Python methods that emit TCL • Some implement standard Hammer “steps” • Some can be vendor-specific steps • Solution: Codify in a “Tool Plugin” 16

Technology Concerns Separated • PDK Concerns • Install directory • Technology files Design Tool • Standard cells, SRAMs, other IP Tech. • Available PVT (Process/Voltage/Temperature) corners • Technology-specific TCL commands/snippets • Include python methods that are included in the flow • Solution: Codify in a “Technology Plugin” 17

Hammer IR Separated • Hammer IR codifies design information Concerns • Also can override tech- and tool-specific settings Design Tool • Can be JSON or YAML (preferred) Tech. • “Namespaces” separate categories of settings (e.g. vlsi.core ) # Specify clock signals vlsi.inputs.clocks: [ {name: "clock", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow vlsi.core.build_system: make # Pin placement constraints vlsi.inputs.pin_mode: generated vlsi.inputs.pin.generate_mode: semi_auto vlsi.inputs.pin.assignments: [ {pins: "*", layers: ["M5", "M7"], side: "bottom"} ] 18

A Quick Example: Power Straps Separated • To specify power straps, need to know: Concerns • DRC rules • Target power dissipation Design Tool • IR drop spec Tech. • Domain areas • Hierarchical also adds physical constraints: X • Tiled modules require pitch-matching X • Easy to make mistakes when reworking Z … Y 19

A Quick Example: Power Straps Separated • Don’t make the designer do math Concerns • Codify design process in tech- and tool-agnostic code Design Tool • Method: Tech. • Determine valid pitches for hierarchical design • Automatically calculate offsets for hierarchical blocks • Generate layout-optimal, DRC clean straps X • Specify intent at a higher-level than length units X Z … • Example: Using ”By tracks” specification Y 20

A Quick Example: Power Straps Separated Concerns Design Tool Tech. Choose power strap strategy par.generate_power_straps_method: by_tracks par.power_straps_mode: generate 21

A Quick Example: Power Straps Separated par.generate_power_straps_options: Concerns by_tracks: track_width: 4 Design Tool Allocate tracks Tech. par.generate_power_straps_method: by_tracks par.power_straps_mode: generate ) S S V , D D V ( 2 = s n a i m o d r e w o 8 p = f s o r n e a i b m m o u 4 tracks d 4 tracks n 2 x s k c a r t 4 = p u VSS o VDD r g r e p s k c a r t 22

A Quick Example: Power Straps Separated par.generate_power_straps_options: Concerns by_tracks: track_width: 4 Design Tool power_utilization: 0.5 Tech. Determine pitch par.generate_power_straps_method: by_tracks par.power_straps_mode: generate n o i t a z l i t i u / p u o r g r e p s k c a t r = h c i t p p u o r G repeat... 4 tracks 8 tracks 4 tracks 6 1 = 5 . 0 / (utilization = 50%) 8 = VSS routing VDD 23