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From UML to SystemC: Intensive signal processing application Jean-Luc Dekeyser dekeyser@lifl.fr http://www.lifl.fr/west/ Y model for SoC design 3 models User applications ISP applications Hardware Target architectures


  1. From UML to SystemC: Intensive signal processing application Jean-Luc Dekeyser dekeyser@lifl.fr http://www.lifl.fr/west/ « Y » model for SoC design � 3 models User applications � ISP applications Hardware � Target architectures Application Architecture � Mapping of applications Association on architectures Models Deployment Compilers � VC � Model separation allows reuse � Typical programming techniques in SoC design

  2. Model Driven Engineering � Model Driven Architecture (MDA) approach for SoC design � PIM to PIM transformation mapping/scheduling � Automatic generation of high-level SystemC specifications from ISP description PIM to PSM transformation � Platform description model of SystemC ISP domain � � Profiling and performance evaluation � Toward SW/HW co-design Modeling at different abstraction levels � Ensures bit accuracy and cycle accuracy � Industrial IP libraries (VIPLibrary:ST, ARM, …) and academic � (SoCLib) The “Y” Model and MDA: Metamodel View ISP-UML hardware (application) architecture use model PIM PIM use model PIM associations PIM - Application and architecture association concepts independently of targeted deployment platforms. - Platform specification PSM PSM concepts Mapping rules Java DPN* interoperability SystemC VHDL Model Model Model Model Model *Distributed Process Network

  3. Model Driven Engineering for ISP Visual specification of application mode using TAU G2 MOF domain UML Profile Metamodel Ptolemy application Internal representation PIM Mapping Refinement rules Platform Platform description description SystemC code generation Internal representation PSM Metamodel execution Model to Model Transformations ISP � SystemC Application High Level UML2 Modeling (UML 2) metamodel hardware ISP metamodel metamodel is defined by save / load is defined by transf. engine hardware UML2 � ISP transformations rules model transformation SystemC transformations transf. rules engine SystemC SystemC metamodel C++ Code

  4. Status � Visual modeling of Intensive Signal Processing Application � Eclpis Plugin � Metamodel and UML profile of ISP � Model to model transformation and code generation UML TAU G2 <-> ISP � ISP -> SystemC � � ISP domain in SystemC ( KPN execution model) � Distributed SystemC runtime Socket � Corba � � Multi abstraction level SystemC simulation Application PIM: ISP Example hydro hydro input1 input1 fft : FFT fft : FFT output1 output1 input1 input1 fv : FV fv : FV coeffV coeffV result result input1 input1 coeff coeff array array input1 input1 <<aolTiler>> <<aolTiler>> norm : Normalization norm : Normalization qd1 : AolTiler qd1 : AolTiler result result pattern pattern input1 input1 input1 input1 lbl : LargeBandRegroup lbl : LargeBandRegroup result result fft : etFFT fft : etFFT result result input1 input1 shortIntegration : Integration shortIntegration : Integration pattern pattern result result <<aolTiler>> <<aolTiler>> qd2 : AolTiler qd2 : AolTiler array array input1 input1 coeffAz coeffAz azimutStabilization : AzimutStabilization azimutStabilization : AzimutStabilization result result input2 input2 output1 output1 input1 input1 longIntegration : Integration longIntegration : Integration result result result result

  5. BiProcessor with SAM <<PassiveComponent>> <<PassiveComponent>> s : SAM s : SAM <<InterconnectComponent>> <<InterconnectComponent>> b : Bus b : Bus <<ActiveComponent>> <<ActiveComponent>> <<ActiveComponent>> <<ActiveComponent>> p1 : Proc p1 : Proc p2 : Proc p2 : Proc

  6. Distributed SystemC in CORBA IPs are available on server hosts � Each IP or IP group must be encapsulated in a SystemC module � (corba_server_if) Transport object : remote method invocation on CORBA bus (set/get � on ports) Clocked modules to support synchronization of distributed IPs � IP 1 IP 2 IP 3 IP 4 IP 5 Client Server 1 Server 2 CORBA Bus SystemC multi-abstraction level What : Connecting together IPs described at different abstraction levels � Why : Easy and fast simulation platform with existing IPs � How : Data conversion and protocol conversion � Construction of level adapters by rule compositions (No library) � � Transformation rules (transformation of the ports) � Association rules (transformation and definition of ports protocols) Module Module 2 1 RT level UTF Simulation module adapter

  7. Future works � A Full « Y-model » � Extend ISP model with control-flow model (esterel) � Hardware hierarchical specification (Syndex oriented) � Mapping specification and optimization techniques � A MDA style � MOF definition of metamodels � MDATransf tool � Mapping rules towards Esterel/scade � PDM of SystemC ISP domain � Multi-language PSM, Multi-PSM Collaborations � UML2.0 Profil � P2I Itea Project � PROTES (Carroll Inria, CEA, Thales) � Standardisation action at OMG � Around SystemC � Collaboration with Irvine (D Gajski) SpecC � TIMA Grenoble (Dynamic scheduling) � Soclib � EuroSoc � ECSI

  8. FDL ’04 in Lille http://www.ecsi-association.org/ecsi/fdl/fdl04/home.htm

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