Faster Adder Circuits for Inputs with Prescribed Arrival Times - PowerPoint PPT Presentation

Faster Adder Circuits for Inputs with Prescribed Arrival Times Ulrich Brenner, Anna Hermann Research Institute for Discrete Mathematics University of Bonn Aussois, 10th January 2018 1 / 14

Boolean Circuits t 0 t 1 t 2 t 3 t 4 inputs ∧ logic gates in B ∨ � ( t 1 ∨ t 2 ) ∧ ( t 3 ∧ t 4 ) � outputs t 0 ∧ � ( t 1 ∨ t 2 ) ∨ ( t 3 ∧ t 4 ) � 2 / 14

Boolean Circuits t 0 t 1 t 2 t 3 t 4 inputs ∧ logic gates in B ∨ � ( t 1 ∨ t 2 ) ∧ ( t 3 ∧ t 4 ) � ( t 1 ∨ t 2 ) ∧ ( t 3 ∧ t 4 ) � � outputs t 0 ∧ � ( t 1 ∨ t 2 ) ∨ ( t 3 ∧ t 4 ) � 2 / 14

Boolean Circuits ◮ A Boolean circuit is the implementation of a logical function using logic gates of a basis B. ◮ Here, B := {∧ , ∨} . t 0 t 1 t 2 t 3 t 4 inputs ∧ logic gates in B ∨ � ( t 1 ∨ t 2 ) ∧ ( t 3 ∧ t 4 ) � ( t 1 ∨ t 2 ) ∧ ( t 3 ∧ t 4 ) � � outputs t 0 ∧ � ( t 1 ∨ t 2 ) ∨ ( t 3 ∧ t 4 ) � 2 / 14

Boolean Circuits ◮ A Boolean circuit is the implementation of a logical function using logic gates of a basis B. ◮ Here, B := {∧ , ∨} . t 0 t 1 t 2 t 3 t 4 inputs ∧ logic gates in B ∨ � ( t 1 ∨ t 2 ) ∧ ( t 3 ∧ t 4 ) � ( t 1 ∨ t 2 ) ∧ ( t 3 ∧ t 4 ) � � outputs t 0 ∧ � ( t 1 ∨ t 2 ) ∨ ( t 3 ∧ t 4 ) � Boolean Circuit Optimization Given a basis B and a Boolean function f : { 0, 1 } n → { 0, 1 } m , find a good circuit computing f over B . 2 / 14

Depth of a Boolean Circuit ◮ Assume that input t i has arrival time 0. ◮ Assume that traversing a gate takes 1 time unit. � + 1. ◮ The arrival time at gate g is a ( g ) = max p ∈ δ − ( g ) � a ( p ) Definition The depth of a circuit C on inputs t 0 , . . . , t m − 1 is the maximum arrival time of any node in C . Example: B = {∧ , ∨} , f ( t 0 , . . . , t 4 ) = t 0 ∧ ( t 1 ∨ ( t 2 ∧ ( t 3 ∨ t 4 ))) 0 0 0 0 0 0 0 0 0 0 t 0 t 1 t 2 t 3 t 4 t 0 t 1 t 2 t 3 t 4 1 1 1 2 2 2 3 3 4 Depth 4 Depth 3 3 / 14

Delay of a Boolean Circuit ◮ Assume that input t i has arrival time a ( t i ) ∈ N . ◮ Assume that traversing a gate takes 1 time unit. � + 1. ◮ The arrival time at gate g is a ( g ) = max p ∈ δ − ( g ) � a ( p ) Definition The delay of a circuit C on inputs t 0 , . . . , t m − 1 with arrival times a ( t i ) ∈ N is the maximum arrival time of any node in C . Example: B = {∧ , ∨} , f ( t 0 , . . . , t 4 ) = t 0 ∧ ( t 1 ∨ ( t 2 ∧ ( t 3 ∨ t 4 ))) 4 2 1 0 1 4 2 1 0 1 t 0 t 1 t 2 t 3 t 4 t 0 t 1 t 2 t 3 t 4 2 3 3 3 5 4 4 6 5 Delay 5 Delay 6 3 / 14

Adder Circuits via And-Or -Path Circuits Addition of two binary numbers ( a n − 1 . . . a 0 ) and ( b n − 1 . . . b 0 ). Essential step: Computing the carry bits c i . Example 1 1 1 0 1 + 1 0 1 0 1 1 1 1 1 1 1 0 0 1 0 4 / 14

Adder Circuits via And-Or -Path Circuits Addition of two binary numbers ( a n − 1 . . . a 0 ) and ( b n − 1 . . . b 0 ). Essential step: Computing the carry bits c i . Example a 0 + b 0 c 1 = ( a 0 ∧ b 0 ) c 1 4 / 14

Adder Circuits via And-Or -Path Circuits Addition of two binary numbers ( a n − 1 . . . a 0 ) and ( b n − 1 . . . b 0 ). Essential step: Computing the carry bits c i . Example . . . a i +1 a i . . . + . . . b i +1 b i . . . . . . c i +1 c i . . . = ( a 0 ∧ b 0 ) c 1 � � c i +1 = ( a i ∧ b i ) ∨ ( a i ⊕ b i ) ∧ c i 4 / 14

Adder Circuits via And-Or -Path Circuits Addition of two binary numbers ( a n − 1 . . . a 0 ) and ( b n − 1 . . . b 0 ). Essential step: Computing the carry bits c i . Example . . . a i +1 a i . . . + . . . b i +1 b i . . . . . . c i +1 c i . . . = ( a 0 ∧ b 0 ) c 1 � � c i +1 = ( a i ∧ b i ) ∨ ( a i ⊕ b i ) ∧ c i � ��� � � ( a i − 1 ⊕ b i − 1 ) ∧ c i − 1 = ( a i ∧ b i ) ∨ ( a i ⊕ b i ) ∧ ( a i − 1 ∧ b i − 1 ) ∨ 4 / 14

Adder Circuits via And-Or -Path Circuits Addition of two binary numbers ( a n − 1 . . . a 0 ) and ( b n − 1 . . . b 0 ). Essential step: Computing the carry bits c i . Example . . . a i +1 a i . . . + . . . b i +1 b i . . . . . . c i +1 c i . . . = ( a 0 ∧ b 0 ) c 1 � � c i +1 = ( a i ∧ b i ) ∨ ( a i ⊕ b i ) ∧ c i � ��� � � ( a i − 1 ⊕ b i − 1 ) ∧ c i − 1 = ( a i ∧ b i ) ∨ ( a i ⊕ b i ) ∧ ( a i − 1 ∧ b i − 1 ) ∨ � ��� � � = t 0 ∨ t 1 ∧ t 2 ∨ t 3 ∧ . . . 4 / 14

Adder Circuits via And-Or -Path Circuits Addition of two binary numbers ( a n − 1 . . . a 0 ) and ( b n − 1 . . . b 0 ). Essential step: Computing the carry bits c i . Example . . . a i +1 a i . . . + . . . b i +1 b i . . . . . . c i +1 c i . . . = ( a 0 ∧ b 0 ) c 1 � � c i +1 = ( a i ∧ b i ) ∨ ( a i ⊕ b i ) ∧ c i � ��� � � ( a i − 1 ⊕ b i − 1 ) ∧ c i − 1 = ( a i ∧ b i ) ∨ ( a i ⊕ b i ) ∧ ( a i − 1 ∧ b i − 1 ) ∨ � ��� � � = t 0 ∨ t 1 ∧ t 2 ∨ t 3 ∧ . . . ⇒ Fast circuits for these functions yield fast adder circuits. 4 / 14

And-Or -Path Optimization Definition An And-Or -path on inputs t 0 , . . . , t m − 1 is a function of type t 0 ∧ ( t 1 ∨ ( t 2 ∧ ( . . . t m − 1 ))) or t 0 ∨ ( t 1 ∧ ( t 2 ∨ ( . . . t m − 1 ))) . t 0 t 1 t 2 t 3 t 4 t 0 t 1 t 2 t 3 t 4 t 5 t 0 ∧ ( t 1 ∨ ( t 2 ∧ ( t 3 ∨ t 4 ))) t 0 ∨ ( t 1 ∧ ( . . . ∨ t 5 )) Definition (Delay Optimization Problem for And-Or-Paths) Let m > 0, inputs t 0 , . . . , t m − 1 and arrival times a ( t i ) ∈ N for i = 0 , . . . , m − 1 be given. Find a circuit realizing an And-Or - path on t 0 , . . . , t m − 1 over the basis {∧ , ∨} with minimum delay. 5 / 14

Example for a Delay-Optimum And-Or -Path Circuit 3 1 4 2 2 3 3 2 3 2 3 1 4 2 2 3 3 2 3 2 4 5 3 4 4 5 4 4 5 6 5 5 7 6 6 8 7 9 10 11 12 Delay 12, number of gates 9 Delay 7, number of gates 12 6 / 14

Known Results for Depth Optimization Lower bound: ◮ Commentz-Walter [1979]: log 2 m + Ω(log 2 log 2 m ) Upper bound: ◮ Grinchuk [2009]: log 2 m + log 2 log 2 m + 3 7 / 14

Lower Bound on Circuit Depth 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 2 2 3 4 Observation Any circuit containing only 2-input gates with n inputs has depth at least ⌈ log 2 n ⌉ . 8 / 14

Lower Bound on Circuit Delay 0 0 1 1 1 2 2 3 4 ◮ Consider any circuit on inputs t i with arrival times a ( t i ). 8 / 14

Lower Bound on Circuit Delay 0 0 1 1 1 a := 2 2 3 4 ◮ Consider any input t i with arrival time a := a ( t i ) > 0. ◮ Replace t i by a full binary tree with depth a . 8 / 14

Lower Bound on Circuit Delay 0 0 0 0 0 0 1 1 1 1 1 a := 2 2 3 4 ◮ Consider any input t i with arrival time a := a ( t i ) > 0. ◮ Replace t i by a full binary tree with depth a . ◮ The tree has 2 a inputs. ◮ This does not change the delay of the circuit. 8 / 14

Lower Bound on Circuit Delay 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 2 2 3 4 i 2 a ( t i ) inputs. ◮ Iterating yields a circuit with W ( t ) := � Observation Any circuit containing only 2-input gates on inputs t 0 , . . . , t m − 1 with arrival times a ( t i ) has delay at least ⌈ log 2 W ( t ) ⌉ . 8 / 14

Known Results for Delay Optimization i =0 2 a ( t i ) . Let W := � m Lower bound: ◮ Huffman [1952] (Binary tree): ⌈ log 2 W ⌉ Upper bounds: ◮ Rautenbach et al. [2006] / Held, Spirkl [2017]: 1 . 441 log 2 W + 2 . 673 ◮ Spirkl [2014]: ⌈ log 2 W ⌉ + 2 � 2 log 2 m + 6 ◮ Here: log 2 W + log 2 log 2 m + log 2 log 2 log 2 m + 5 9 / 14

Characterization of And-Or -Paths via Truth Assignments t 0 t 1 t 2 t 3 t 4 t 7 10 / 14

Characterization of And-Or -Paths via Truth Assignments t 0 t 0 t 1 t 2 t 2 t 3 t 4 t 4 t 7 t 7 10 / 14

Characterization of And-Or -Paths via Truth Assignments t 0 t 1 t 1 t 2 t 3 t 3 t 4 t 4 t 7 10 / 14

Characterization of And-Or -Paths via Truth Assignments t 0 t 1 t 1 t 2 t 3 t 3 t 4 t 4 t 7 Observation The output is true ⇐ ⇒ There is an input t k of an Or gate s.t. ◮ t k generates a true signal and ◮ each And gate after t k propagates the true signal. 10 / 14

Well-Known Recursion Strategy t ′ t ′′ t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 11 / 14

Well-Known Recursion Strategy t ′ t ′′ t ′ t ′′ t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 11 / 14

Well-Known Recursion Strategy t ′ t ′′ t ′ t ′′ t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 11 / 14

Our Proof Strategy t ′ t ′′ t ′ t ′′ t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 Theorem (Brenner, H.) 2 d − 1 Fix a delay bound d. Given inputs t with weight W ( t ) ≤ d log 2 ( d ) , we can compute a circuit for an And-Or -path on t with delay d. Proof idea: Induction on d , extending Grinchuk’s proof [2009]. 11 / 14

Critical Part of the Proof Inductive step 2 d For inputs t with weight W ( t ) ≤ , we can ( d +1) log 2 ( d +1) compute a circuit for an And-Or -path on t with delay d + 1. large t ′ t ′′ Proof idea: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 ? d d + 1 Inductive step. 12 / 14