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Energy Harvesting: Strategies for ultra low power consumption and reliability. Antonio Rubio and Francesc Moll Universitat Politcnica de Catalunya (UPC) Electronic Engineering Department Barcelona, antonio.rubio@upc.edu CHIST- ERA Conference


  1. Energy Harvesting: Strategies for ultra low power consumption and reliability. Antonio Rubio and Francesc Moll Universitat Politècnica de Catalunya (UPC) Electronic Engineering Department Barcelona, antonio.rubio@upc.edu CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  2. Overview 1. Introduction 2. Energy harvesting experiments 3. Low power consumption: adiabatic logic experiments 4. Reliability requirements: new architecture experiments 5. Conclusions CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  3. 1. Technology evolution in terms of energy Landauer’s limit 10 6 times ISSCC 2011 Trends Report CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  4. 1. TECHNOLOGY EVOLUTION AND LIMITS POWER (W) 10 0 Technology limits � • Sensitivity to internal 2000 and external perturbances 2002 10 -3 • Memory robustness 2004 DRAIN 2006 W GATE fin H fin SOURCE 2010 t ox L G 10 -6 2012 OXIDE SUBSTRATE � 10 -9 neuron 10 -12 Fundamental Limits 10 -15 10 -15 10 -12 10 -9 10 -6 10 -3 10 0 10 3 Delay, (s) J.. Meindl , “Low power microelectronics: retrospective and prospective” Proc. IEEE, 1995 CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  5. In the field of Energy-autonomous wearable systems both Energy scavenging devices and Drastic circuit principles for ultra-low power are necessary, and require balanced research efforts CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  6. 2. Energy harvesting Energy harvesting, experiences: • Piezoelectric generation • Inductive generation CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  7. Piezoelectric conversion Example of piezo measurements in a shoe F 1 S 1 S 1 L. Mateu, F, Moll, "Optimum piezoelectric bending beam structures for energy harvesting using shoe inserts", Journal of Intelligent Material Systems and Structures, vol. 16, October 2005, pp. 835-845. CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  8. Inductive harvesting generators L. Mateu, C. Villavieja, F. Moll, "Physics-based time-domain model of a magnetic induction microgenerator", IEEE Trans. on Magnetics, vol 43, no. 3, March 2007, pp. 992-1001. CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  9. 3. Adiabatic logic: an alternative for reducing power consumption Advantage: important reduction of power consumption Drawbacks: increase of complexity, pulsed power supplies, performances slow down CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  10. CONCEPT OF ADIABATIC SWITCHING CONVENTIONAL SWITCHING ADIABATIC SWITCHING R R C C T 2 /2 2 /2 Energy dissipated in R: CV DD Energy dissipated in R: (RC/T)CV DD Making T>RC the dissipation energy in R can be lowered. If T  ∞ dissipation  0. CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  11. CONCEPT OF ADIABATIC SWITCHING Experimental example: The implementation of a ternary multiplier using Adiabatic CMOS logic. 0.7 m CMOS technology (1997) circuit # power delay PDP devices Conventional CMOS 8x8 2308 18 mW 38 ns 700 pJ bits multiplier (3.3 volts) Adiabatic ternary 5x5 trits 3850 4 W 17 s 70 pJ multiplier (3.3 volts) D. Mateo and A. Rubio, IEEE Journal of solid-state circuits, vol. 33, no. 7, July 1998. CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  12. CONCEPT OF ADIABATIC SWITCHING Preliminary results about future technologies technology circuit # power delay PDP devices 18 nm CMOS (*) Conventional CMOS 16x16 bits 1 20000 1 50 multiplier (0.9 volts) 10 nm FinFET (*) Adiabatic 16x16 bits multiplier 2.8 1 1000 1 (0.6 volts) (*): Models from TRAMS project, EC FP7 248789 CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  13. Reliability requirements and new reliable architectures are a key issue for future low voltage ultra-low power technologies CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  14. RELIABILITY PROBLEMS IN LOW VOLTAGE SYSTEMS CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  15. RELIABILITY ARCHITECTURAL SOLUTIONS FOR NEAR 0dB SNR • Probabilistic logic, Markov Random Fields, Stochastic computation • Von Neumann works, NMR strategy CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  16. HIGH RELIABILITY EXPERIMENTS (I) TL: A new probabilistic logic based on port redundancy and information coherence V DD =150 mV = 60 mV Garcia-Leyva , L. et al, “A new probabilistic design methodology of nanoscale digital circuits”, CONIELECOMP’2011 Results from TRAMS project, EC FP7 248789 CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  17. HIGH RELIABILITY EXPERIMENTS (II) An adaptive 4LRA redundant architecture 70% of saving in redundancy N. Aymerich, S. Cotofana , A. Rubio, “Adaptive Fault- Tolerant Architecture for Unreliable Device Technologies”, IEEE Nano 2011 Results from TRAMS Project EC FP7 248789 CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

  18. Conclusions • Combined research efforts on both harvesting energy generation and ultra low power design systems should pave the research road next years. • New development of harvesting generators should be investigated • Ultra low power design techniques as adiabatic logic, reversible logic, probabilistic and stochastic computing could be key factors in future technology • Special attention has to be dedicated to reliability: new reliable and robust computer architectures in low voltage near 0-dB SNR scenario has to be investigated and developed CHIST- ERA Conference 2011, “Green ICT, towards zero power ICT” Cork September 5 th 2011

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