EDA Challenges Technology allows for 100M transistors on a chip - PDF document

Policy-Based RTL Design Bhanu Kapoor and Bernard Murphy Atrenta Inc. Atrenta Inc | Page 1 EDA Challenges • Technology allows for 100M transistors on a chip • Good but point EDA solutions exit • Time consuming due to complexity of designs • Discover problems after hours and days of run • Early decisions affect entire design process • Guiding a given RTL towards various design constraints remains a big challenge • Reliable RTL design process Atrenta Inc | Page 2 1

Challenges in Product Development Knowledge Gap Design commitment Available Design Information Design Cycle Atrenta Inc | Page 3 Policy-Based RTL Design • Policies that guide the creation of efficient RTL • Target design needs early in the design cycle • Conflicting issues known early • Long simulation and synthesis not always needed • Disseminate expert knowledge • Towards Golden RTL Atrenta Inc | Page 4 2

Model for Policy Management • Policy – Lint & Reuse [OpenMORE & STARC] – RTL Signoff – Design Timing, Testability, Power – Verification – SoC Integration • Rule Groups • Rules • Policy Application • Policy Creation • Analysis and Report Atrenta Inc | Page 5 Rules and Groups Rule Group Rule Atrenta Inc | Page 6 3

Parameterized Policies Max levels of logic Max fanout Atrenta Inc | Page 7 Policy Engines • Fast high-level synthesis • Traversal Engine • Cycle-based simulator Atrenta Inc | Page 8 4

Analysis & Report • Guiding from detection of issues to solution • Various formats for reporting variations on summary - scoring - • Software management of underlying issues manage by design units, files, design as a whole - manage the state of issues - mechanisms to control reporting - Atrenta Inc | Page 9 Policies DFT Tool Timing Policies Power Area RTL Code Clocks Reuse Verification Atrenta Inc | Page 10 5

Levels of Logic Cross-probe to schematic Cross-probe to RTL code Levels of Logic Violation Atrenta Inc | Page 11 Atrenta Inc | Page 11 Fanout Violations Atrenta Inc | Page 12 Atrenta Inc | Page 12 6

Resolving Issues By Simulation Only one driver active at a time for tri-state buses 'DWD /RJLF 6\VWHP (QDEOH /RJLF /RJLF Atrenta Inc | Page 13 Atrenta Inc | Page 13 Multiple Clock Domain Issues module abc module abc Signals from multiple clock domains always @(posedge clk_1) begin // clk domain1 always @(posedge clk_1) begin // clk domain1 converging to a common logic-- q1 <= din; q1 <= din; multi-transition, multi-sample signals end end endmodule //end of module abc endmodule //end of module abc module xyz module xyz f1 …. dout …. q2 din q1 always @(posedge clk_2) begin // clk domain2 always @(posedge clk_2) begin // clk domain2 q2 <= q1; q2 <= q1; clk_1 end end endmodule //end of module xyz sig1 endmodule //end of module xyz ….. ….. clk_2 always @(posedge clk_2) begin //synch always @(posedge clk_2) begin //synch dout <= q2; dout <= q2; f2 end end assign f2 = func2(q1,..); assign f2 = func2(q1,..); assign f1 = func1(dout, ..); assign f1 = func1(dout, ..); assign sig1 = f1 & f2; assign sig1 = f1 & f2; Module boundaries Atrenta Inc | Page 14 Atrenta Inc | Page 14 7

Clock Synchronization Problems module synch… module synch… … … always @(posedge clk1) begin always @(posedge clk1) begin qsync d q q <= d; q <= d; E z <= w; z <= w; ready <= dready; ready <= dready; End End … … zsync w z // generate sync signal // generate sync signal always @(posedge clk2) begin always @(posedge clk2) begin rds <= ready; rds <= ready; CK1 pass <= rds; pass <= rds; CK2 end end pass ready … … // synchronize // synchronize CK2 always @(posedge clk2) begin always @(posedge clk2) begin if (pass) qsync = q; if (pass) qsync = q; … … z-bus not correctly synchronized • zsynch = z; zsynch = z; May not be found in simulation • end end Impact • Yield issues – Field failures – Atrenta Inc | Page 15 Clock Synchronization module abc module abc always @(posedge clk_1) begin // clk domain1 always @(posedge clk_1) begin // clk domain1 Enable of destination flop is driven by ar <= a;br <= b; r<=ready ar <= a;br <= b; r<=ready a synchronized signal end end endmodule //end of module abc endmodule //end of module abc a ar module xyz module xyz as …. …. always @(posedge clk_2) begin // clk domain2 always @(posedge clk_2) begin // clk domain2 rr <= r; rr <= r; clk_2 clk_1 end end br b always @(posedge clk_2) begin // clk domain2 always @(posedge clk_2) begin // clk domain2 bs rs <= rr; rs <= rr; end end always @(posedge clk_2) begin // clk domain2 always @(posedge clk_2) begin // clk domain2 clk_2 clk_1 if (rs) as<= ar; if (rs) as<= ar; if (rr) bs<= br; if (rr) bs<= br; ready rs end r rr end ….. ….. endmodule //end of module xyz endmodule //end of module xyz clk_2 clk_2 clk_2 Atrenta Inc | Page 16 Atrenta Inc | Page 16 8

Testability Issues module src1… module src1… Signals from mixed edge domains • … … combined always @(posedge clk) always @(posedge clk) q1 = d q1 = d … … Create problems for scan insertion – module src2… module src2… … … • Not found until ATPG check always @(negedge clk) always @(negedge clk) q2 = g q2 = g • Impact … … module aggregate… module aggregate… Wasted implementation cycles – … … always @(posedge clk) always @(posedge clk) Schedule delays – mix = q1 & q2 mix = q1 & q2 … … d CLK mix src 1 g CLK src 2 aggregate Atrenta Inc | Page 17 Clock Gating Use of gated clocks to � selectively turn on/off various units in the design Functional All large functional units are � Unit use enabled clock Clock All banks of memory controlled � by enabled clock Large fanout flops use � enabled clocks Enable Atrenta Inc | Page 18 9

Pre-computation An Suggest the use of pre- � computation Bn Example: A > B where A and A>B � B are 32-bit buses, result can be obtained by An-1 examining A[31] and B[31] and rest of the computation gated based on this result B1 Atrenta Inc | Page 19 Summary • Policy-Based RTL Design • Policy Management • Elements of Policy Policy elements Policy engine Analysis and reporting • Examples of pertinent design issues Atrenta Inc | Page 20 10