eda 2 asic Systems 2.5/3D ICs Technical AND Business Considerations Herb Reiter, eda2asic Consulting, Inc. herb@eda2asic.com, 1-408-981-5831 MEPTEC Luncheon, June 13, 2012
eda 2 asic AGENDA • Introduction • A few market numbers • Why develop 2.5/3D solutions ? • What’s different in the 2.5/3D ecosystem ? • 2.5/3D products TODAY • Opportunities for MEPTEC members • Appendix: Additional market data
eda 2 asic Herb Reiter’s Background Magister (= MBA) & MSEE in Austria Synplicity, Structured ASIC Tools ‘80: National Semi Europe , PLD Mktg 1980 ReShape, IC Design Flow ‘83: National Semi U.S., ASIC Mktg Gradient, Temp Analysis, ICs Flomerics, Temp Analysis, PCB ’86: MBA, San Jose State AMD, Opteron Mktg to EDA ’89: VLSI Technology GDA, Design Services Biz Plan 1990 Alliances, ASICs & ASSPs Mktg Takumi, DFM Tools & Services Innovative Silicon, ZRAM-IP S3 Group, Analog & M/S IP ‘97: ViewLogic, ASIC Alliances ‘98: Synopsys, Semicond. Alliances Philips, Clockless IC Design 2000 ‘00: Barcelona Design, Alliances Mentor, C RTL Synthesis Mephisto DA, Analog Sizing ’02: eda 2asic Consulting, Inc. Ciranova, Analog Layout Biz Dev for New Technologies GeorgiaTech, SiP Noise Analysis Stanford: Continuing Education Soitec & SOI Consortium, SOI 2010 GSA, 3D-IC Working Group 10 years of bridging the gap between SEMATECH, 3D Enablement Ctr EDA tools and ASIC design challenges
eda 2 asic Market Numbers
eda 2 asic 2016 Market Size Forecast Systems need to get faster Auto AND consume less power . 5% 2.5/3D-ICs can integrate CAGR sub-systems, even entire systems at lower power, Industrial higher speed and eventually 6% Computer $2.74T Systems CAGR also lower system cost. 7% 8% CAGR (2011- ’16) CAGR If 2.5/3D-ICs capture addit’l Electronic 10% of the systems market, Systems t hey’ll grow semiconductor 5 X 8% revenues by 50 % !!! CAGR EDA tools for modeling, Consumer Comms planning & partitioning, 7% CAGR implementation and $517B Semi verification of ICs have a 12% CAGR significant impact on the cost-effectiveness of 3D semiconductor solutions. Semi’s 50 X Relatively minor investments Sources for Systems & Semi #s: in EDA tools, IP blocks and Databeans, Gartner, die-level IP will enable these Cadence Design Systems semiconductor vendors to > $10B EDA & IP Spring 2012 contribute big to faster and ??? CAGR lower power systems !
eda 2 asic Quarterly EDA Revenues Silicon IP IC Physical PCB / MCM CAE Services Total EDA Revenues http://www.edac.org/mss/stats_mss.jsp in CY 2011: http://www.edac.org/mss/MSS_2012_Category_Definitions_FINAL.pdf USD 6.13 Billion
eda 2 asic ~ 30% of Semiconductor Revenue is… http://www.semi.org/en/node/41166
eda 2 asic Why Develop 2.5/3D Solutions ?
eda 2 asic Key Motivators Reduce system cost Reduce power dissipation Reduce form factor Increase system complexity/user friendliness Increase performance per Watt Increase reliability Decrease time-to-market Decrease NRE and risk
eda 2 asic Challenges for Feature Size Shrinking Wafer Fab cost Cost per gate Variability Risk, TTM Design Cost Mask Cost Yield Variations Source: International Business Strategies 2010
eda 2 asic Energy per Operation (64 bit words) DDR3 4.8 nJ/word 128 pJ/word Optimized DRAM core 400 pJ/cycle MIPS 64 core 11 nm 0.4 V core 200 pJ/op 45 nm 0.8 V FPU 38 pJ/Op 1.9 nJ/Word SERDES I/O 128 pJ/Word 20 mV I/O 512 pJ/Word LPDDR2 1 cm / high-loss interposer 300 pJ/Word 45 pJ/Word 0.4 V / low-loss interposer 7 pJ/Word On-chip/mm TSV I/O (ESD) 7 pJ/Word TSV I/O (secondary ESD) 2 pJ/Word Dr. Paul Franzon, NCSU, June 2012
eda 2 asic Cost Comparison for Mixed-Signal ICs Heterogeneous integration on one die is usually expensive 3D stacking reduces cost for heterogeneous integration Courtesy: Borkar, Intel Yuan Xie, Penn State Univ.
eda 2 asic TSV Enabled Benefits Design Automation Conference, San Francisco, June 2012
eda 2 asic What’s Different in the 2.5/3D Eco-System?
eda 2 asic Application Specific Requirements Data Centers Mobile Devices Battery Life in minutes http://www.ilshayeb.com/?p=1494 http://www.lbl.gov/Science-Articles/Archive/data- center-energy-myth.html Battery Life and System Price !!! Operating & Cooling Cost !!!
Systems eda 2 asic Changes Needed for 2.5/3D-ICs Business Model profit & responsibilities sharing SYSTEM-level H/W + S/W Wafer Manufacturing p lanning & partitioning,… TSV etch, -fill, w- probe,… Pathfinding t hinning, RDL,… Die-InterPoser-Pkg-Board Thin Wafer Handling co-design, die-level IP, DFT,... bond-, debond, ship,.. Single Die, Stack, In-System Test and Assembly v erification, debug,… KGD, (partial) stack testing,… Materials for d ie, interposer, substrate, package,…
eda 2 asic EDA Vendors Driving Standards Libraries, IP, Dice,… Standards . Designers Design Design tools Rules, Libraries, Models EDA Design Vendors Files and Test Programs Modeling tools Manufacturers Standards for Fab, Assembly, Test Hand-off Criteria
eda 2 asic We Need a Light … Standards Organizations - Capture common requirements - Help setting R & D priorities - Manage pre-competitive JOINT development efforts - Lead consensus towards standards - Educate users, proliferate & update standards - Domestic standards organizations, e.g.: - …and many more standards organizations in foreign countries
eda 2 asic MISSION: Accelerating the next technology revolution Research Development Manufacturing 3D Enablement Center Members: ADI, Altera, ASE, Invensas, LSI, NIST, ON Semi, Qualcomm 3D Interconnect Program Member: Hynix SEMATECH Core Members: CNSE, Global Foundries, IBM, Intel, Samsung, TSMC SEMATECH Standards Dashboard at: http://wiki.sematech.org/3D-Standards
eda 2 asic Closed vs Open Innovation Principles CLOSED OPEN The smart people in the field work Not all smart people in the field work for us. We need to 1 work with smart people inside AND outside our company. for us. To profit from R&D we must discover External R&D can create significant value; internal R&D 2 it, develop it and ship it ourselves is needed to claim some portion of that value. If we discover it ourselves, we will 3 We don’t have to originate the research to profit from it. get it to market first. The company that gets an innovation Building a better business model is better than getting to 4 to the market first, will win. the market first. If we create the most and best ideas If we make the best use of internal and external ideas, 5 in industry, we will win. we will win. We should control our IP so that our 6 We should profit from others’ use of our IP, and we should competitors don’t profit from our ideas. buy others’ IP whenever it advances our business model. http://www.inventorium.org/2012/04/10/open-innovation/oi/
eda 2 asic In the Good Old Times … Total COST and Time-to-Market were the dominant criteria for technology selection Development- Cell-based/COT and Per-Unit Cost FPGA Gate Array Production Volume Use FPGA Use Gate Array Use Cell-based/COT Time to Market: 1 Week to Months Months to Quarters Quarters to Years
eda 2 asic Technology Selection Today Examples for important technology selection criteria Unit Cost Bandwidth AND Latency Impact on System Cost Power NRE Dissipation Application 1 2 3 4 5 Specific ! Time to Heterogeneous Functions Market Formfactor Risk Elements Resources Internal / External
eda 2 asic Tomorrow: 2.5/3D System Integration Source: Rao Tummala, Georgia Institute of Technology, 3D Systems Packaging Research Center, Oct 2010
eda 2 asic 2.5 / 3D Products TODAY
eda 2 asic Technology Comparisons http://www.design- reuse.com/articles/exit/?id=1 SoC and SiP, 4887&url=http%3A%2F%2Fw ww.commsdesign.com%2Farti combined in a PoP cle%2FprintableArticle.jhtml% 3FarticleID%3D196700054 PoP cross-section from www.ifixit.com PoP SiP Interposer 3D/TSV Package Thickness Power Dissipation Access Time Bandwidth Industry Readiness Memory Logic limited o.k. good best
eda 2 asic
eda 2 asic Copper Pillars vs Solder Bumps http://www.edn.com/article/print/521939-Die_to_die_bonding_using_copper_pillars.php
eda 2 asic Wide I/O Standard Standardized by JEDEC 42.6 Published in December 2011 Twice the bandwidth of LPDDR2 at the same power Mobile HD video: 12.8 MB/sec 4 channels, each 128 data bits 1200 total connections 1.2V CMOS signal levels Pad-pitch 40 x 50 microns Boundary scan to test I/C Locations of thermal sensors Exact mechanical dimensions (defined by JC 11) Courtesy: Intel and JC 42.6
eda 2 asic Wide I/O Standard JEDEC ( JC 42.6 ) released Q4, 2011 the first Wide I/O Standard TWICE the Bandwidth at the same Power Dissipation as LPDDR2 Sophie Dumas, Drivers: Samsung, Elpida, Hynix, Micron, STEricsson Qualcomm, TI, Intel, AMD, ST, Apple, Advantest and others Wioming Test-Chip http://eda360insider. wordpress.com/2011/ 12/14/3d-week-wide- io-sdram-network-on- chip-multicore-tsv- asynchronous-logic- 3d-soc-stack-from- cea-leti-and-st- ericsson-hits-all-the- advanced-notes-can- you-say-tour-de- force/
Recommend
More recommend
