EDA Challenges in Systems EDA Challenges in Systems EDA Challenges - PowerPoint PPT Presentation

EDA Challenges in Systems EDA Challenges in Systems EDA Challenges in Systems EDA Challenges in Systems Integration Integration J. A. G. Jess NSF EDA Workshop July 8 and 9 2009 July 8 and 9, 2009

Why should IC- Why should IC -EDA and EDA and Electronics Systems Electronics Systems Manufacturers move closer? Manufacturers move closer? Manufacturers move closer? Manufacturers move closer?  With Moore’s Law electronic systems move to become IC’s – off-chip communication b C’ ff hi i i moves on-chip facing IC designers with systems communication legacy i i l  Electronics Systems market is roughly six times the market of IC’s – interesting for EDA to have the ESM’s as customers

Two Paradigms: Two Paradigms: Two Paradigms: Two Paradigms: Heterogeneous Heterogeneous - - Homogeneous Homogeneous homogeneous homogeneous heterogeneous heterogeneous A few (at times frequently Many specialized (optimized) Computing replicated) general compute replicated) general compute Computing compute engine types engine types (X86 API,…) A few universally used A few universally used M Many specialized i li d Communi- standard bus protocols “communication fabrics” cation (PCIe, AMBA AXI,…) Standard (virtual) Many different memory Memory Random Access Memory types, designer in control supported by caches of memory policy

Attempt of Attempt of a a Taxonomy Taxonomy Heterogeneous Homogeneous  Good Compute Performance  Compute Performance to to Power Ratio (MOPs/Wsec) Power Ratio medium (improving!) but unpredictable  Small “Bill of Material”  BoM medium to large  BoM medium to large (BoM, e.g. area) (BoM e g area)  Lack of Flexibility  Very flexible through programming on “Virtual  Large NRE cost, limited re- a ge N cost, ted e Machine” use  Extensive re-use of SW and HW HW

Sample Hardware Sample Hardware Architecture Mobile Device Architecture Mobile Device (~2005) (~2005) ( 2005) ( 2005) Display Display RF/IF RF/IF 2Mp Camera Baseband Applications Module DSP & ARM Proc. ARM NAND Card Card Burst Cellular NAND Mobile Flash SDRAM NOR RAM 256 Mb 256 Mb 128/256 Mb 128/256 Mb 32 Mb 32 Mb 16 Mb 16 Mb

Devices sharing Interconnect Devices sharing Interconnect Communication Display (“Bus”) Interface Speaker RF/IF RF/IF Mike Mik xMp xMp CPU DSP CPU DSP CPU DSP Camera Core Core Core Module ge bridg More More NAND Mobile Burst Cellular Functions NAND NAND Peripherals Peripherals Flash Fl h SDRAM SDRAM NOR O RAM Card 32 Mb 16 Mb 256 Mb 128/256 Mb

Heterogenity vs. Homogenity Heterogenity vs. Homogenity Processor Arch. Homogenious Processor Arch. ect Arch. Interconne ect Arch. ct Arch. Interconnec Interconne I Heterogenious Processor Arch.

Basic Challenges Basic Challenges  How to assign performance metrics to the co-ordinates of the cube?  Given those metrics, how to establish tools providing decision support for designers providing decision support for designers (and roadmap makers)?

“Systems Integration” “Systems Integration”  A large portion of the design effort is concerned  A large portion of the design effort is concerned with matching the on-chip and inter-chip communication- and memory performance with the specifications h ifi i  Communication is critical for Timing and Power  How deal with contention on shared interconnect?  H d l ith t ti h d i t t?  Stability of system modes and mode-transitions?  Verification is hampered by the lack of formal  Verification is hampered by the lack of formal design documentation on system level  Up to now there seems to be little tooling support Up to now there seems to be little tooling support – lots of manual code development & guessing

Thank you!