Discussion of what to show at ITK-SC meeting 1
What has been asked for • Current status, near term plans • From today and older slides, draft to be circulated before meeting • First pass at costs, schedule to production, and a list of open issues to address • Need input now and over next 2 weeks – Put my personal guesses/questions down to start discussion, which I think should go page-by-page 2
Costing • Assume they are only asking for material costs (not including manpower) • Dominated near-term by ASICs – Will need to estimate number and cost of MPW and full wafers submissions (NRE and per wafer) • ABCn130, HCC, SPP, SCR, AMISx • For most other things, depends strongly on substructure – Should we use old generic numbers?? • What do we assume about barrel and end-cap geometry? Maybe costs per m 2 of strips or for strawman?? 3
Schedule • I would assume that schedule is also driven by ASICs – First need to agree on estimated number of MPW and full wafer submissions to get to final ASIC – Check against TDR date (Dec. 2014) and production dates (2015-2018) – Discuss what the options are if they are inconsistent • From our past experience (hopefully being faster/more likely to succeed on each iterations), I would guess after receiving wafers: – First ASICs tested with probing started: 1-3 months – First working hybrids: 2-4 months – First working modules: 4-6 months – Multi-modules:~12 months • This assumes no surprises (which hasn’t ever happened) • We also have to have some idea on a list of decisions to be approved before a given MPW and full wafer submission can be made – Powering (DC/DC vs SP) for barrel and end cap, track trigger, DCS, barrel and end-cap layouts 4
My Personal List of open questions within the strip modulue working group and its connection to the rest of the ITK- SC structure 5
ASICs • What are the timescales and plans for submissions? Will there be another round of MPW submission of full ABC130 and HCC prior to large scale submission? What is the impact on the schedule? – If we go for a MPW, how many ASICs do we get? Can we make enough hybrids/modules to test full chain before/after irradiations? – For final production, how do we make the support ASIC? MPW, parts of ABCn130 wafer, or separate wafers? • What is the mechanism for getting approval for the submissions (MPW and full wafer)? Where is the money coming from? How do we optimize money vs. time (risk of failure with earlier submissions) • What redundancy do we want in the ASICs, how does the segmentation of hybrids (1 vs 2 column hybrids) effect the HCC (layout and number per module)? 6
Hybrids (1) • What is the ideal layout (1 vs 2 columns) for the 130 nm versions? • What redundancy do we want? I assume it is not copies of all clock and command line as it has large impact on size of hybrid (material). But what about data?? • What is the spec for maximum HV? I assume 500 V+ safety (600 V), matches to current cable train and needed estimated signal. What can be done to reduce size of HV filter or can it moved onto bus tapes? • To start a layout, need to know a best guess at the number of lines needed, and rough estimate on the sizes of ABC130, HCC, and any on-board powering ASICs. Would also need to discuss optimal locations of HCC and powering ASICs. – Layout would be useful to sketch prior before “finalizing” pad layout as it may inform on ideal pad locations, sizes, and overall ASIC size as the size might be determined by what is bondable • How can material further be reduced while still being producible? Reduction of SMD capacitors, removal of shield layer (staves/petals), hatching/thinning of metal layers, …. • What specifications can we use for track/gap, via lands, layer thicknesses to still have a high yield, throughput and not get locked into one foundry? How do we put large scale production (SMD/ASIC attach, bonding, and testing) into industry? 7
Hybrids (2) • Are there big gains from leaving kapton for more aggressive, high performance substrates (for example Endicott LCD)? Is the material reduced? Is it easier to get hybrids from industry with C4 bump bonded ASICs? Are they gains in costs/throughput in the production chain? Are the gains in bond-ability by having any integrated PA on hybrid worth the costs and potential load capacitance increases? – CMS is currently doing a market survey of these kind of processes. It would make sense to have a task-force of people from ATLAS in a common venture with CMS looking at these high performance substrates. At a minimum need to gauge costs, availability, material reduction. As material in substrate is propriatary would involve tests for radiation lengths, inactions with other materials in build, etc. – Would need funding/manpower to start in this direction if desired. • Personally, I think it would be a mistake not to look into these developments as big leaps may be possible 8
Modules (Single/Multi) • How do we optimally make backplane connections? – Bonding or glue? If glue, how do we improve contact? • How do we isolate HV between modules (staves/petals)? • Is it possible to gang HV together to reduce services? Would it be possible to switch bad modules out of such a ganging? • What is the best method for low impedence connections for shields/ground references? • Do long barrel designs put multi-drop clock/command at risk? 9
Service Bus • What specifications for track and gaps, shielding, connection details can we change to increase number of firms which can produce tapes, reduce costs, increase yields? How much would that cost in extra material? • How much material can be removed from shields? • How does long barrels effect producability/foundry availability/costs? • How does topology in end caps affect producability? Does powering choice effect this? 10
End of Substructure (GBT, versatile link, controller, DCS) • Has any thought gone into final packaging? What technology do we want to use? Is the end of substructure just an extension of service bus or is in a multi-layer hybrid? Does the packaging allow to redistribution of signals to make bus tapes simpler? • I assume it is powered separately. How does it effect the power-on/off sequences? How does powering choice effect thinking? 11
Power (SP, DC/DC) • What still needs to be done to learn as much as we can from the current ASICs? • What do we want to study with new ASICs? What needs to be includes in ABC130 and HCC to do achieve this? • When do we make decision and how? How important is it that barrel and end cap have same solution? 12
DCS On-detector • What do we have to include in next ASICs/hybrids/end of substructure to make informed choice for final system? • What do we want to monitor using DCS within the SMWG? What is the minimum set needed for safety vs. monitoring? • Does DCS imply separate power/clock/data feeds for HCC? 13
Irradiations • Is full irradiation programme (sensors, materials, ASICs, modules) within work package? If so, we need a lot of help to coordinate effort. • What do we want to irradiate and when? When do we need to start SEU studies? Who can perform them? 14
Interactions needed with sensor working group (1) • Inputs needed – Specifications for expected currents, load capacitances, signal at end of lifetime of detector • Sets needed performance of FE and allows for optimization of power of analogue section • Need further info from layout (simulation WG??) for expected segmentation of all sensor types – Did we confirm going to 2 or 4 segments for all positions now? – Needed to set data/command/clock formats/protocols – Status on understanding of issues with FZ1 sensors breaking down after handling • We have done trialling and have the breakdown occurs after only vacuuming the sensor down (no glue) 15
Interactions needed with sensor working group (2) • With group need to set/discuss: – Locations of bond pads, bias ring openings • With simulation group, need to determine optimal layout of stereo sensor (dead areas and overlap) – Making back-side HV contacts • What is possible? Gold plating a section of sensor’s backplane, gold stud bonds + silver epoxy, wire bonding to a tab, or using silver epoxy – Isolation of neighbouring sensors • What is being done with IBL, phase 2 pixels? Peak or kapton inserts between them? Coating edges with Alumina (thin edges) or BCB? Have tests ever been done to determine needed spacing in air between sensors as a function of bias voltage? – Setting operational voltage • For S/N studies, we know 500 V is sufficient and matches to current HV cable train. More voltage gives extra performance and headroom but at the cost of replacing cables, added heat from sensors – Need to set this to layout end of sub-structure, bus and hybrids. 16
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