Digital System-On-Chip components at ESA components at ESA ASIC - PowerPoint PPT Presentation

Digital System-On-Chip Digital System-On-Chip components at ESA components at ESA ASIC technology platforms and converters Standard microprocessor components Components with dedicated DSP function Roland Weigand, Laurent Hili European Space Agency Microelectronics Section MEWS 24, Tsukuba, Japan Microelectronics Section (1) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA Outline • ASIC platforms – Current technologies (180 – 150 nm) – New technologies: 90 nm (UMC), 65 nm (ST) – Converters: ADC, DAC, HSSL • Standard SPARC V8 microprocessor components – LEON2: AT7913E, AT697 – LEON3: SCOC3 – LEON4: NGMP – QUADLION • Components with dedicated DSP functionality – FFTC: Fast Fourier Transform Co-processor – AGGA4: GNSS baseband processor for GPS, Galileo, Glonass, Compass – CWICOM: CCSDS Wavelet Image Compression ASIC – HPDP: High Performance Data Processor – Smart image sensors for sun-sensors and star-trackers Microelectronics Section (2) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA The ESA Microelectronics Section http://www.esa.int/TEC/Microelectronics 8 permanent staff Directorate of Technical and Quality Management Electrical Engineering Department Data Systems Division 293 staff ESTEC ESOC HQ 1310 staff 368 staff European Space Research 207 staff and Technology Centre ESRIN ESAC R&D, engineering and test 73 staff centre 2251 staff in total Microelectronics Section (3) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA Current ASIC platforms • Atmel ATC18RHA 180 nm (see Atmel presentation) • DARE (Design Against Radiation Effects) library on UMC 180 nm – High total dose tolerance, mixed signal capability available – Area and power consuming library, limitations in memory compiler – 90 nm planned, but funding currently on-hold • LFoundry 150 nm (Germany) – Mixed signal, 5V IO and NVM available, no radiation hardened library – ESCC Space process capability study with DLR and Tesat http://www.dlr.de/qp/en/desktopdefault.aspx/tabid-3091/4699_read-6881/ → LFoundry Germany seems to be bankrupt → activity on hold ? • Ramon Chips (Tower 180 nm, Israel) – SEU hardened library available for 180 nm, 130 nm in preparation – Mixed signal capability, embedded NVM TBD – Device qualification possible (MIL-STD-883 lot acceptance) – Export licence and commercial availability to be clarified • XFAB 180 nm (Germany) – Mixed signal, 5V IO and NVM available – Radiation hardened standard cell library currently not available – No space experience so far, but radiation evaluation and rad-hard library planned Microelectronics Section (4) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA Motivation for DSM programme  Deep Sub Micron ASIC technologies are key for establishing European capabilities in the domain of: Digital telecom payloads   Improve European competitiveness on mobile processors and digital sub channelisers (narrowband processors) Enable technology for future multimedia satellites and flexible payloads with active  antennas (broadband processors) Earth Observation payloads   SAR, altimetry, interferometry  Mass memories High Speed Serial Links (HSSL > 1Gbps)   Navigation payloads Wideband signal generation   The DSM programme is managed and co-financed by ESA and CNES Microelectronics Section (5) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA Motivation for DSM programme • Microelectronics technology developments are driven by telecom needs for future broadband and versatile payloads (mobile, multimedia, HDTV) • Higher ASIC complexity – 20 … 30 Millions gates – Higher clock data path ( ≥ 400 MHz) – Higher power dissipation per ASIC ( ≥ 15 Watts) – Higher pin count package (flip chip ≥ 1600 pins) – Higher data rate interfaces (HSSL 6.25 Gbps) • Faster and power efficient ADC and DAC – Analog input bandwidth 500 MHz instead of 150MHz – ADC and DAC data rate ≥ 1.5 Gsamples/s – High complexity antenna systems / beamforming » Number of ADC ≥ 200 » Number of DAC ≥ 200 – Need to reduce the power consumption per converters » Max power per ADC ≤ 1.5 Watt » Max power per DAC ≤ 1.5 Watt Microelectronics Section (6) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA Interfacing between DSM ASIC and broadband ADC / DAC SERDES 6.25 Gbps High Speed Serial Link (6.25 Gbps) ASIC (65 nm) Broadband / low power ADC Broadband / low power DAC 1.5 Gsps 1.5 Gsps 12b 12b Baseband processing ADC DAC - Sub channeliser 12b 12b - Beam forming - Switch 2 x 750 Msps 2 x 750 Msps Quatuor device (65 nm) Quatuor device (65 nm) Quad high speed link 4 x 6.25 Gsps Microelectronics Section (7) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA Broadband ADC / E2V Performances Features (EV10AS180):  10 bits ADC  Single Tone Performance @ Fs=1.5Gsps :  integrated 1:1/2/4 Demux (selectable)  SFDR = -60 dBFS, ENOB = 8.5 Bit;  2.2 Gsps conversion rate (full BW) SNR = 55 dBFS at Fin = 750 MHz @-12 dBFS  1.7 Watt  SFDR = -60 dBFS, ENOB = 8.4 Bit;  low latency 4 clock cycles SNR = 53 dBFS at Fin = 1800 MHz @-12 dBFS  Broadband Performance:  LVDS outputs  0.5 Vpp differential input (100 ohms)  NPR = 44 dB at -13 dBFS  Power supplies: 5.2V, 3.3V and 2.5V Optimum Loading Factor in 1st Nyquist  Ci-CGA225 package  NPR = 43 dB at -13 dBFS  B7HF200 SiGeC technology from Infineon Optimum Loading Factor in L-band  100 Krads radiation tolerant Microelectronics Section (8) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA Broadband DAC / E2V Features (EV12DS130):  12 bits DAC Performances  integrated parallel Mux 4:1 / 2:1 (selectable)  3Gsps conversion rate  NPR @ -14dB loading factor, Fs = 3Gsps  6GHz analog output BW  1 st Nyquist (NRZ/NRTZ) NPR=49db ENOB=9.7 bits  1.3 Watt  2 nd Nyquist (NRTZ/RTZ) NPR=44db ENOB=8.8 bits  low latency 4 clock cycles  3 rd Nyquist (RF) NPR=42db ENOB=8.4 bits  NRZ, RTZ, narrow RTZ, RF modes  100 Krads radiation tolerant  LVDS inputs  1 Vpp differnetial output (100 ohms)  Power supplies: 3.3V digital, 3.3V and 5V analog This activity is under CNES contract  Ci-CGA225 package  B7HF200 SiGeC technology from Infineon Microelectronics Section (9) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA Broadband DAC / E2V Comparison between NRZ, NRTZ, RTZ and RF modes Max output power versus frequency over the 3 Nyquist zones Microelectronics Section (10) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA ST 65nm CMOS technology • 65nm-LP CMOS from ST France : European technology, ITAR free • 65nm CMOS commercially qualified in 2007 • 65nm CMOS Core Process : – Dual / Triple Gate Oxides – Dual / Triple Threshold Voltages for MOS Transistors – 7-9 Full Copper Dual Interconnect Levels – Low K • Characteristics : – 750 kgates/mm2 – 2GHz stdcells – 5.7nW/(MHz x gates) – 1.25-7.5GBit/s HSSL modules  ST Rad Hard offer based on CMOS 65nm-LP commercial process  Reliability and Radiation maximisation performed at design stages Microelectronics Section (11) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA ST 65nm / reliability enhancement Systematic application of ST Design-in-Reliability (DiR) methodology (focusing HCI and NBTI) with dedicated tools for aging simulations • Specific layout rules for reliability enhancement • Study of tighter controls at process level • Analysis of reliability figures from Std qualification • ST has build an industrial flow which allows a full coverage of reliability effects all along the product value chain. • Reliability tests will be performed during ESCC evaluation phase to confirm it Microelectronics Section (12) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA ST 65nm / radiation enhancement • Rad-hard capabilities measured under ESA contracts (ST 130nm, 90nm, 65nm and 45nm) – No current increase seen up to 100krad(Si) TID • SEL-free with Deep-N well process option • SEE/SETs fault injection techniques for Digital and Analog blocks sensitivity analysis – Usage of existing Robust cells, TMR – Hardening of clock-trees against SETs – Shadowing of configuration registers + scrubbing – Development of Rad-Hard new cells – Layout techniques Microelectronics Section (13) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use

MEWS 24 Digital System-On-Chip components at ESA ST 65nm CMOS technology / Space offer Comparison for a DFFX3 Skyrob Skyrob Corelib (drive 3) (Rad Hard) (Fast) (Commercial) SEU rate 1E-9 1.8E-9 2E-7 Robust x110 seu/bit/day (Geo) Robust x250 shielding 100mils Al Timing 750 500 500 Set-up + delay (ps) 50% slower As fast Area 26 23 13 um 2 X2 area X1.7 area Energy 4 3.8 2.2 pJ X1.8 X1.7 Microelectronics Section (14) 14. Oct 2011 ESA UNCLASSIFIED –For Official Use