Development of Optical Interconnect PCBs for High-Speed Electronic Systems – Fabricator’s View 2011 IBM Printed Circuit Board Symposium Raleigh, NC, USA November 16 th 2011, Time: 10:00-10:30am Speaker: Marika Immonen TTM Technologies
Outline • Motivation – Need and Challenges • Roadmap for Intra-System Optical Interconnects • Optical PCB Development – Development Objectives and Target Applications – Polymer Waveguide Technology and Channel Termination – Test Vehicle Description and Results • Summary • Future Work
Motivation • Growing bandwidth demand – Many studies show 40-50% annual growth in global Internet traffic – High-definition video and high-speed broadband penetration and consumer IP traffic responsible for majority of the traffic growth. [Cisco Visual Networking Index 2008] – Enablers: Smart & media devices, social networks, 3D content, Cloud computing and services • Increasing gap between network traffic and hardware development – Network traffic 2x in 18 months – Server I/O 2x in 24 months • Standard initiatives for higher data rates – IEEE 802.3ba 40/100G ratified June 2010 1 st Gen will use 10 Gbps signaling – – Improvements in size, power, and diff pair count leads increasing data rates per lane – 25 Gb/s [IEEE & OIF CEI 25G/28 G]; 10-20 Gb/s [Infiniband, & Fiber Channel] Sources: Cisco Visual Networking Index - Forecast and Methodology 2007-2012, IEEE 802.3 100G Copper BP TF; Optical Interconnecting Forum (OIF)
Copper Backplane Challenges • Some challenges for 25 Gb/s/lane implementation – Fabrication: Copper roughness, back drilling stub removal, moving to low & ultra-low loss material set & processes – Well controlled Electrical/Mechanical parameters • Flatness; Hole locations; Thickness variations • Copper geometries & tolerance vs. Impedance, Attenuation, Propagation delay – Power Consumption: Goal to keep less 1.5x of power of 10Gb/s [OIF CEI 25/28] => Challenging – Cost: Ultra-low loss materials 3-6x FR4; additional chips (equalization, amplification) increase cost – Termination: challenging to design (low cross- talk, noise) , difficult to maintain form factors & high density – Need clear understanding of yield detractors: yield/cost vs. design trade-offs Copper will be used as long as competitive alternatives are not available 4
Optics Will Be A Solution to Mitigate Challenges Speed is only one metric, the main drivers for optics are capacity over distance, lower power comsumption, bandwidth density and cost Cost of a Terapipe Power consumption of 10 Tbps Power Consumption for Over 5 Years Electrical vs. Optical Router Interconnect Operating Costs 20% reduction in 98% reduction • High-Speed interconnect is costing power consumption in cost more power and money • A terapipe, bi-directional Tbps interconnect – Copper transceivers: $3500/year • Each 100G link consumes 10W each (1kW/Tb) – Traditional Optics: $700/year • Each 10G XFP (10km) consumes 2W (200W/Tb) – VCSELs: $70/year • Each 10G VCSEL consumes 0.2W (20W/Tb) – Silicon Photonics: $70/year • Each 10G Si-Pho link consumes 0.2W (20W/Tb) – Kotura, “The Path to 1 TbE” – IEC “Optical Backplane Roadmap” 86/374/DC 2010 Ethernet Summit Feb-2011 5
Optics Will Be A Solution to Mitigate Challenges Bandwidth Density [Gbps/mm2] Optical=6x electrical [Gbps/mm2] • Cross-Talk – Copper: Higher frequency signals => wider pitch: 3x signal speed => 3x pitch – Frequency 2x leads 6 dB increase in crosstalk – Photons: Isolation of few microns enough • Photons do not suffer EMI • Optical High Speed Design Challenges, Cost and Complexity Electrical – Signal traces with highly controlled impedance, via holes, and connectors are adding cost – Photons: Frequency independent loss and design TTM IBM Microstrip Core [µm] Pitch [µm] Density Optical vs. [Gbps/mm] copper 50x50 250 40 1,4 50x50 100 100 3,5 Waveguide 35x35 62,5 160 5,6 6
Optical Interconnects for Short Reach Applications “Intra - Box” “Out -of- Box” • Applications per link length IEC TC86 field IEC TC86 field for standardization for standardization – Within Data Center: 100-300 m Opto-electronic module Opto-electronic module – Rack-to-Rack: 20-30 m – Most links in DC – Intra-Rack : < 10 m – Intra-Box links: < 1-2m – FO links emerging Optical backplane Optical backplane • Server/HPC Environment Fibre cable Fibre cable Optical connector Optical connector – “Everyone needs optical interconnect with low power, low cost and high density” • One size fits all does not meet the Optical circuit board Optical circuit board Discussion field in JWG9 Discussion field in JWG9 requirements in this environment ＜商品化段階＞ ＜商品化段階＞ • Requirements vary per application – Link length vs. cost vs. power consumption vs. density Image: Sunway BlueLight MPP, National Supercomputer Center in Jinan, China Image: Avago – Various physical link implementations, connector and device form-factors needed -- Potential BW off ASIC -- $/Gbps -- Watt/Gbps or pJ/bit -- $/Inch of board edge – IEEE Next-Gen 100Gb/s Optical Ethernet Study Group 7
Optical Intra-System Link Evolution RACK-TO-RACK BOARD-TO-BOARD BACKPLANES AND ON-BOARD 1990 1995 2005 2010 2012 2015 Density, Capacity, Complexity 3 rd Gen Fiber-Waveguide Backplanes Fiber Backplanes Active Waveguide 2 nd Gen Optical Backplanes Fiber Optic Cables Engines Fiber-less Engines 1 st Gen 1-10 Gb/s (Parallel) (Highly parallel) Flex Shuffle (SFP+) 5-25 Gb/s Backplane > 12.5 Gb/s (Fiber flex) Fiber links (Single) Number of links, Integration level, Functionality 8
Embedded Waveguide Architecture and Building Blocks 1. Optical Engines with Interface to waveguides 1 1 2. Optical Channel Tx/Rx : Tx/Rx : VCSEL, 3. Optical Connectors with VCSEL, DRV, PD, functions e.g. 90° beam DRV, PD, TIA deflection TIA CARD CARD Logic IC Logic IC 2 2 3 3 2 BACKPLANE 9
Development Objectives Optical/Electrical Circuit Board Technology • Hybrid passive PCB with optical and electrical interconnects • Optical manufacturing methods and tolerances compliant with conventional PCBs • Passive optical alignment and simple assembly (optical device to connector, connector to board, connector to connector) • Pluggable optical connectors with reasonable alignment tolerance • Cost comparable to electrical solution • High reliability and long-term stability 10
Optical Waveguide Routing Layout And Components • Optical Routing Requirements – Point-to-point links Electrical Optical – Link length: 130-200 mm – Cascading bends CARD • Negative and positive cascading 90° bends • Multiple cascading bends per link CARD • RoC min 17 mm – Crossovers CARD • Waveguides intersect in one or more positions along the channel • Angles 130° to 160° (40° to 70°) BACKPLANE/ MIDPLANE Network Storage Midplane R.Pitwon et al .: “Design and Implementation of an Electro -Optical Backplane with Pluggable In- Plane Connectors”, SPIE 7607 -18, 2010.
Production Test Vehicle Description • Optical/Electrical Mixed Signal Board – Generic test bed with multiple waveguide passive components – Designed for parallel optics l =850 nm VCSEL /PD 12-channel unidirectional or 4+4 bidirectional Engines – Optical waveguide signal layer • Multi modal type with numerical aperture (N.A.) matching MMF • Square step index profile in multiple core sizes and pitch – Core: 25x50µm 2 , 50x50µm 2 , 70x50µm 2 ; Pitch: 250µm, 100µm – Optical circuit layout with multiple design features & functions : Straight, cross-overs, bend waveguides – Channel termination and optical I/O coupling • Flat end I/O and 45° out-of-coupling micro-mirrors – Variations in board construction and layer count • 2+W and 2+W+2 (W=waveguide) • High-Tg Std. loss FR-4 (baseline); Mid-loss halogen-free base 12
Fabricated OE PCB Module : 2+W+2 Embedded Optical Layer Connector test sites Construction : 2+W+2 Waveguides Optical I/O – Board build: 2+W+2 (W=waveguide) – Board thickness 2.0 mm – Optical layer thickness: 115 µm – Waveguide width: 25’ 50’ 70 µm – Channel pitch: 100’ and 250 µm – Integrated 45-deg beam couplers 13
Waveguides W=25’ 50’ 70 µm, Pitch=100 µm, 250 µm • Physical Characterization – Parameters: Dimensions, uniformity, alignment accuracy , surface roughness. Tools: Optical, LSCM, SEM L/S 25/100 µm, Pitch 125 µm L/S 50/250 µm, Pitch 250 µm L/S 50/50 µm, Pitch 100 µm L/S 70/30 µm, Pitch 100 µm L/S 50/200 µm, Pitch 250 µm 14
Side Wall Roughness vs. Channel Loss λ = 850 nm, Core 100µmx100µm, n core =1,56, n clad =1,49 (NA=0.46) Source: It-Infomation Technology 45 (2003), 79-86 Cladding ”Macro” roughness (L=240 µm) Core ”Micro” roughness : < 5 nm Ra < 30 nm Core ”Macro” roughness (L=300 µm) Ra < 25 nm White light interferometer (Wyko NT 2000) 15
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