COOL Interconnect COOL Interconnect Low Power Interconnection - PowerPoint PPT Presentation

COOL Interconnect COOL Interconnect Low Power Interconnection Technology Low Power Interconnection Technology for Scalable 3D LSI Design for Scalable 3D LSI Design Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto TOPS Systems Corporation Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi National Institute of Advanced Industrial Science and Technology COOL Chips XIV COOL Chips XIV

Outline Outline １． Background ２． 3D LSI • Current 3D LSI technology ３． Heterogeneous Multichip 3D LSI: COOL System ４． COOL Interconnect • Protocol • Interface Circuit Design ５． Test Chip ６． Summary ７． Future work COOL Chips XIV COOL Chips XIV

Background Background Always increasing power consumption Low power technology ・ Clock gating ・ Dual Vt ・ Static back-gate bias Reasons f Reasons for or the the increase increase of of ・ Dynamic back-gate bias energy consumptio energy consumption ・ Power cut-off ・ Very high number of units ・ DVFS technology ・ Low voltage ・ Increase in features Consumption ・ Amount Amount of of data an data and d requirement in mobile devices Communi mmunication s cation spee eeds ds (800mW-1000mW) Consumption in IT devices ・ Appliances (IT) Leakage current increase ・ Network switches due to semiconductor ・ Data Center miniaturization IT 機器における国内総電力消費量と A breakthrough in the reduction of LSI energy consumption is needed CO2 排出量予測（ 2006 ～ 2050) ・ Can’t increase freq Utilization Wall ・ Only 8 cores are used ・ the number of active transistors within any given semiconductor ＜ Multicore miniaturization ＞ chip has exponentially decreased accordingly with its miniaturization Classical Leakage- 8 Cores@2GHz scaling limited Scaling 32nm Transistors S 2 S 2 4 Cores@2GHz ・ Frequency S S 65nm Dark Silicon ・ Consumption (Cap) 1/S 1/S 【 Challenges 】 Consumption （V dd ） 1/S 2 ～1 ・ Energy consumption limit 4 Cores@4GHz ・ Increase in leakage current 32nm Utilization 1 1/S 2 ・ Operation frequency limit The key is not in the miniaturization, is in the efficient use of its transistors COOL Chips XIV COOL Chips XIV

3D LSI 3D LSI Different technologies like common circuit logic, memory, etc. can be freely stacked to surpass Moore’s Law More than simple integration, the processor architecture also change to Standardization of inter- mitigate the Utilization Wall, the chip communication Memory Wall, the Power Wall and the ・ Easy to design ILP Wall ・ Easy to dest Through-silicon via （TSV） I/O Stacked LSI Memory Ideal based on Processor application Current state requirements Scalable 3D LSI 【Advantages of a scalable 3D LSI】 －Low power consumption －High level integration 4 layer stacked memory cell 8Gb 3D DRAM ISSCC2010 Unity Semiconductor 129 chips stacked in a 3D LSI －High performance ISSCC2009 Samsung ISSCC2010 Keio U/ Prof. Kuroda －Short-to-market cycle －Flexibility －Low cost COOL Chips XIV COOL Chips XIV

Current 3D LSI Technology Current 3D LSI Technology Through-silicon via （TSV） 3D integration technology that uses microbump bonding and adhesive injection Memory Main stacking methods: • Wafer on Wafer Processor • Wafer on Chip • Chip on Chip Ｉ / Ｏ COOL Chips XIV COOL Chips XIV

Heterogeneous Multichip 3D LSI: Heterogeneous Multichip 3D LSI: COOL System COOL System Low power heterogeneous Multichip/Multicore Microprocessor Distributed software technology that architecture designed for 3D stack effectively drives the hardware chips Shared bus Interface logic Peripheral Chip Heterogeneous Multichip/Multicore Distributed processing Memory Scalable interface technology for low power 3D LSI chips COOL Chips XIV COOL Chips XIV

COOL Interconnect COOL Interconnect ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology Multilayer IP COOL Interconnect Interface I/O Data (C) converter Scalable bus I/O Bus arbiter (B) Logic layer Logic layer I/O interface logic (A) Chip ID Q D Circuit layer Interface driver Circuit layer D Q D Q Fabrication Process of Physical layer Physical layer 1600 TSV in 40x40 array COOL Chips XIV COOL Chips XIV

COOL Interconnect COOL Interconnect ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology Shared bus (1600 TSV) Interface logic COOL Chips XIV COOL Chips XIV

Protocol (1/2) Protocol (1/2) ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology Interconnection type ： Shared bus Communication model ： Multi-Master / Multi-Slave （ No of Master chips ： Max 16, Slaves ： Max 16 ） Protocol ： 3-stage pipeline － S0 : Request phase － S1 : Address / command transmission phase － S2 : Data transfer phase COOL Chips XIV COOL Chips XIV

Protocol (2/2) Protocol (2/2) ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology Signal type Description bus_clock - Bus clock Data transfer throughput ： 1 cycle bus_reset - Bus reset Data transfer latency ： 2 cycles bus_req_m(15:0) S0 Request Master Arbitration model ： Dual distributed － Bus-Master bus_req_s(15:0) S0 Request Slave － Bus-Slave bus_s_stat(15:0) S0 Slave Status Transfer mode ： single, burst 、 lock bus_command(3:0) S1 Command bus_address(31:0) S1 Address bus_destination(3:0) S1 Destination bus_lock S1 Bus lock COOL Interconnect‘s data COOL Interconnect‘s data bus_data(1023:0) S2 Data signals consist of 1024 out of bus_data_valid(6:0) S2 Data Valid signals consist of 1024 out of bus_ready S2 Data Ready 1600 TSV 1600 TSV bus_error S2 Data Error Through TSV’s these signals reach all chips within the 3D LSI stack and communicate using an implemented common interface logic COOL Chips XIV COOL Chips XIV

Interface Circuit Design Interface Circuit Design ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology Q D 0.70 14.0 0.664 Driver and reciver circuit consumption x12 D Q 0.60 0.562 12.0 0.526 0.512 0.504 0.498 0.494 0.493 D Q 0.50 10.0 [W@50MHz/1600pins] Power Consumption Noise [VnS] 0.480 Interface driver 0.470 0.460 0.449 0.40 8.0 0.434 0.427 0.414 0.385 Receiver cirucit consumption 0.30 6.0 Comparison with current 5.90 interconnection technology 0.20 4.0 2.97 Cool DDR ‐ 2 (1) Interconnect 1.59 1.46 0.67 mm 2 8.64mm 2 0.10 2.0 Circ. Area I/O 0.73 Noise 0.48 0.36 0.28 4 mm 2 4 mm 2 0.00 0.0 Consumpt 246.5 mW (max) (2) 576 mW X1 X2 X3 X4 X8 X12 X16 X20 6.4 GB/s 6.4 GB/s Bandwidth Driver Size Freq 50 MHz 400 MHz Driver circuit optimization through simulation Driver circuit optimization through simulation (1) DDR-2 PC-6400 COOL Chips XIV COOL Chips XIV (2) Estimation

Test Chip Test Chip ・ Bandwidth ： 6.4GByte/sec ＠ 50MHz ・ Inter-chip connection ： 1600 TSV ・ Model ： Multi-Master / Multi-Slave Shared bus Master （ CPU ）： Up to 16 chips Slave （ Memory/IO ）： Up to 16 Chips Technology TSMC0.25um ・ Interface are ： 4.67mm 2 Interface circuit ： 0.67mm 2 (14%) 8.3 ｍｍ TSV area ： 4mm 2 (86%) TEG 5 ｍｍ 5 ｍｍ 0.2 ｍｍ 2 ｍｍ I/O Same area pad 2.16 ｍｍ TEG TEG 5 ｍｍ 5 ｍｍ 6 ｍｍ (a) Conventional I/O (b) TSV area (4mm 2 ) TSV array 2.16 ｍｍ area (4mm 2 ) Scalable 3D LSI chips interface verification and test Logic TEG COOL Chips XIV COOL Chips XIV

Summary Summary • Scalability of 3D LSI designs will play a crucial role in extending the silicon road-map for the next generation of microprocessor IPs • We presented a working model of a standard interconnection bus for 3D LSI units that provides scalability as well as high performance and low power consumption • Implementing a standard way of inter-chip communication common challenges can be avoided or completely solved. • COOL Interconnect provides the necessary versatility to design 3D LSI efficiently made for the application with a short-to-market cycle and easy fabrication process COOL Chips XIV COOL Chips XIV

Future Work Future Work • Increased power densities that can result from carelessly placing one computational block over another • Find ways to collaborate with open innovation business partners to create a new standard COOL Chips XIV COOL Chips XIV

Cool System Innovator Cool System Innovator This research is supported by the New Energy and Industrial Technology Development Organization (NEDO) COOL Chips XIV COOL Chips XIV