CPSC 121: Models of Computation Instructor: Bob Woodham woodham@cs.ubc.ca Department of Computer Science University of British Columbia Lecture Notes 2009/2010, Section 203 CPSC 121: Models of Computation
Menu February 5, 2010 Topics: Additional Combinational Circuits (cont’d): — Adders and Decoders Pre-class reading: Today: Lab 4, Lab 5 (when available) Reminders: Online Quiz 6 (deadline 9:00pm Sun, Feb 7) Lab 5 next week (pre-lab worth marks) 1st Midterm Wednesday, February 10, 7:00–8:00pm Assignment 2 due Friday, February 12, 17:00 READ the WebCT Vista course announcements board Bob’s course office hours, Friday, 10:30–noon, ICCS 119 www: http://www.ugrad.cs.ubc.ca/~cs121/ WebCT Vista: http://www.vista.ubc.ca CPSC 121: Models of Computation
4-Bit Adder Consider the following high-level design for a “chip” for adding 4 bit integers a and b The 4 bit output s = a + b a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 c in 4−bit adder c out s 3 s 2 s 1 s 0 We’ll need (and the figure shows) two more wires: 1 additional input, c in , and 1 additional output, c out CPSC 121: Models of Computation
4-Bit Subtractor a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 1 FA FA FA FA c out s 3 s 2 s 1 s 0 CPSC 121: Models of Computation
Detecting Overflow in n-Bit Binary Addition Case 1: Adding 2 unsigned integers Check if the last carry, c n − 1 , is one Case 2: Adding 2 signed integers A simple check of last carry, c n − 1 , doesn’t work RECALL: Ignoring carry is key to 2’s complement CPSC 121: Models of Computation
Overflow in n-Bit Signed Binary Addition Let s = a + b Note 1: It’s not possible to produce overflow when adding integers of opposite sign (i.e., when the MSBs of a and b differ). The result, s , is either less positive than the most positive of a and b or less negative than the most negative of a and b (i.e., it’s closer to zero) Note 2: There are two kind’s of overflow: The result is too positive (i.e., a > 0 , b > 0 , s < 0). In this 1 case, the MSBs are, respectively, a n − 1 = b n − 1 = 0 ; s n − 1 = 1 The result is too negative (i.e., a < 0 , b < 0 , s > 0). In this 2 case, the MSBs are, respectively, a n − 1 = b n − 1 = 1 ; s n − 1 = 0 CPSC 121: Models of Computation
Overflow in n-Bit Signed Binary Addition (cont’d) We can put this into a truth table: a n − 1 b n − 1 s n − 1 Overflow 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 By inspection of the truth table, we see we get overflow if and only if a n − 1 = b n − 1 and b n − 1 � = s n − 1 . Thus, a proposition for overflow is ( a n − 1 ↔ b n − 1 ) ∧ ( b n − 1 ⊕ s n − 1 ) CPSC 121: Models of Computation
Overflow in n-Bit Signed Binary Addition (cont’d) We can implement this as a circuit: a n−1 b n−1 overflow s n−1 CPSC 121: Models of Computation
Decoder A decoder is a circuit that accepts an n-bit binary code (aka an address ) and converts it into (up to) 2 n unique outputs. That is, exactly one of the 2 n outputs is set to 1 and all the rest are set to 0. CPSC 121: Models of Computation
A Simple Decoder Example Suppose our Central Processing Unit (CPU) accepts instructions in which 2 bits encode which one of 4 arithmetic operations to perform ( add, sub, mult, div ) Our decoder must accept the 2-bit code as input and set the appropriate output to 1 Once again, we proceed via a truth table CPSC 121: Models of Computation
A Simple Decoder Example Let the 2-bit code be xy codes outputs x y add sub mult div 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 CPSC 121: Models of Computation
A Simple Decoder Example Let the 2-bit code be xy codes outputs x y add sub mult div 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 With 2-bits, there are 4 codes. CPSC 121: Models of Computation
A Simple Decoder Example Let the 2-bit code be xy codes outputs x y add sub mult div 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 With 2-bits, there are 4 codes. Fill the diagonal with 1s, 0 the remaining entries CPSC 121: Models of Computation
A Simple Decoder Example Let the 2-bit code be xy codes outputs x y add sub mult div 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 With 2-bits, there are 4 codes. Fill the diagonal with 1s, 0 the remaining entries NOTE: We are designing this decoder. The codes are not predefined for us CPSC 121: Models of Computation
A Simple Decoder Example (cont’d) We have the following four propositions: ≡ x ∧ y add sub ≡ x ∧ y ≡ x ∧ y mult div ≡ x ∧ y and the circuit: x add sub mult div y CPSC 121: Models of Computation
Example: Arithmetic Overflow Re-Visited Quick Review: So far, we’ve dealt with 3 cases: Unsigned addition. (Check c out ) 1 Signed addition. (Circuit based on a n − 1 , b n − 1 , s n − 1 ) 2 Signed subtraction. (Circuit based on a n − 1 , b n − 1 , s n − 1 ) 3 But, there’s a 4th case: Negation 4 Recall, for n-bit signed integers, the numbers represented range from − 2 n − 1 to 2 n − 1 − 1 The negation of − 2 n − 1 can not be represented Again, we get overflow CPSC 121: Models of Computation
Example: Arithmetic Overflow Re-Visited A circuit to check for this case of overflow is quite simple. We detect the case b = − 2 n − 1 = 1000 . . . 0 2 explicitly b 0 b 1 b 2 overflow b n−2 b n−1 CPSC 121: Models of Computation
Example: Arithmetic Overflow Re-Visited In order to choose between the 4 overflow conditions, we design a 2-bit code, c 1 c 0 , as follows: c 1 c 0 operation 0 0 unsigned addition 0 1 signed addition 1 0 signed subtraction 1 1 negate b Think of these 2 bits as “control bits” CPSC 121: Models of Computation
Example: Arithmetic Overflow Re-Visited Now, here’s the circuit: CPSC 121: Models of Computation
A Circuit of Moderate Complexity Control bits: 00 = unsigned addition 01 = signed addition 10 = signed subtraction 11 = negate b (ignore a) CPSC 121: Models of Computation
More Gate Tricks Let a 1 , a 2 , . . . , a n be n Boolean variables a 1 ⊕ a 2 ⊕ . . . ⊕ a n = 1 if and only if the number of 1s in the n-bit binary number a 1 a 2 . . . a n is odd Note 1: If the number of 1s is odd then the number is said to have odd parity Note 2: Determining a propositional formula for odd parity based on truth tables and Sum–of–Products (SOP) methods is quite difficult/tedious (when n is large) Note 3: Suppose only 2-input XOR gates are available. We can implement n-input XOR either as a “chain” or as a “tree” of 2-input XOR gates CPSC 121: Models of Computation
8-Input MUX for Full-Adder c out Consider the truth table and 8-input MUX a b c in c out 0 0 0 0 0 0 0 1 0 0 1 0 0 2 0 1 0 0 1 3 c out 0 1 1 1 0 4 1 0 0 0 1 5 1 6 1 0 1 1 1 7 1 1 0 1 1 1 1 1 a, b, c in CPSC 121: Models of Computation
MUX Designs: Now and in the Future MUXes are used to build truth table lookup implementations of combinational circuits There are technologies that make the creation of very large lookup tables quite feasible (and effective when combined with MUX-based design) Examples include: Read Only Memory (ROM), (one-time) Programmable 1 ROMS (PROMS), Erasable Programmable ROMS (EPROMS), etc. Programmable Logic Arrays (PLAs) 2 Gate Array Devices 3 Standard Cells 4 CPSC 121: Models of Computation
Combinational Circuits: Summary A circuit element is a combinational device if: it has one or more digital inputs 1 it has one or more digital outputs 2 there is a functional specification that gives the value of 3 each output for every possible combination of valid input values there is a timing specification that gives an upper bound on 4 the required time for the device to compute the specified output values from an arbitrary set of stable, valid input values CPSC 121: Models of Computation
Combinational Circuits: Summary A set of interconnected elements is a combinational device if: each circuit element is a combinational device 1 every input is connected to exactly one output or to some 2 vast supply of 0s and 1s the circuit contains no directed cycles 3 CPSC 121: Models of Computation
Combinational Circuits: Summary Combinational devices are: discrete 1 memoryless (valid outputs always reflect current inputs) 2 noise free 3 CPSC 121: Models of Computation
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