CPSC 121: Models of Computation Instructor: Bob Woodham woodham@cs.ubc.ca Department of Computer Science University of British Columbia Lecture Notes 2008/2009, Section 203 CPSC 121: Models of Computation
Menu February 6, 2009 Topics: Overflow in n-Bit Binary Addition/Subtraction (revisited) (More) Examples (cont’d) Reading: Next: Epp 3.1, Theorem 3.4.1 (page 157), Representation of Integers (pages 159–163), Epp 3.6, and 3.7 Reminders: On-line Quiz 7 deadline 9:00pm February 8 Assignment 2 due Friday, February 13 (by 17:00) Marked Assignment 1 available in tutorials Midterm exam Tuesday, February 24 (evening) READ the WebCT Vista course announcements board CPSC 121: Models of Computation
4-Bit Adder Consider the following high-level design for a “chip” for adding 4 bit integers a and b The 4 bit output s = a + b a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 c in 4−bit adder c out s 3 s 2 s 1 s 0 We’ll need (and the figure shows) two more wires: 1 additional input, c in , and 1 additional output, c out CPSC 121: Models of Computation
Detecting Overflow in n-Bit Binary Addition Case 1: Adding 2 unsigned integers Check if the last carry, c n − 1 , is one Case 2: Adding 2 signed integers A simple check of last carry, c n − 1 , doesn’t work RECALL: Ignoring carry is key to 2’s complement CPSC 121: Models of Computation
Overflow in n-Bit Signed Binary Addition Let s = a + b Note 1: It’s not possible to produce overflow when adding integers of opposite sign (i.e., when the MSBs of a and b differ). The result, s , is either less positive than the most positive of a and b or less negative than the most negative of a and b (i.e., it’s closer to zero) Note 2: There are two kind’s of overflow: The result is too positive (i.e., a > 0 , b > 0 , s < 0). In this 1 case, the MSBs are, respectively, a n − 1 = b n − 1 = 0 ; s n − 1 = 1 The result is too negative (i.e., a < 0 , b < 0 , s > 0). In this 2 case, the MSBs are, respectively, a n − 1 = b n − 1 = 1 ; s n − 1 = 0 CPSC 121: Models of Computation
Overflow in n-Bit Signed Binary Addition (cont’d) We can put this into a truth table: a n − 1 b n − 1 s n − 1 Overflow 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 By inspection of the truth table, we see we get overflow if and only if a n − 1 = b n − 1 and b n − 1 � = s n − 1 . Thus, a proposition for overflow is ( a n − 1 ↔ b n − 1 ) ∧ ( b n − 1 ⊕ s n − 1 ) CPSC 121: Models of Computation
Overflow in n-Bit Signed Binary Addition (cont’d) We can implement this as a circuit: a n−1 b n−1 overflow s n−1 CPSC 121: Models of Computation
Summary: Arithmetic Overflow (So Far) Quick Review: So far, we’ve dealt with 3 cases: Unsigned addition. (Check c out ) 1 Signed addition. (Circuit based on a n − 1 , b n − 1 , s n − 1 ) 2 Signed subtraction. (Circuit based on a n − 1 , b n − 1 , s n − 1 ) 3 But, there’s a 4th case: Negation 4 Recall, for n-bit signed integers, the numbers represented range from − 2 n − 1 to 2 n − 1 − 1 The negation of − 2 n − 1 can not be represented Again, we get overflow CPSC 121: Models of Computation
Overflow in n-Bit Binary Negation A circuit to check for this case of overflow is quite simple. We detect the case b = − 2 n − 1 = 1000 . . . 0 2 explicitly b 0 b 1 b 2 overflow b n−2 b n−1 CPSC 121: Models of Computation
Example: Arithmetic Overflow Re-Visited In order to choose between the 4 overflow conditions, we design a 2-bit code, c 1 c 0 , as follows: c 1 c 0 operation 0 0 unsigned addition 0 1 signed addition 1 0 signed subtraction 1 1 negate b Think of these 2 bits as “control bits” CPSC 121: Models of Computation
Example: Arithmetic Overflow Re-Visited Now, here’s the circuit: CPSC 121: Models of Computation
A Circuit of Moderate Complexity Control bits: 00 = unsigned addition 01 = signed addition 10 = signed subtraction 11 = negate b (ignore a) CPSC 121: Models of Computation
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