Comparison of topside contact layouts for power dies embedded in PCB - PowerPoint PPT Presentation

Comparison of topside contact layouts for power dies embedded in PCB ESTC 2016, Grenoble Chenjiang Y U 1 , Cyril B UTTAY 2 , Éric L ABOURÉ 1 , Vincent B LEY 3 , Céline C OMBETTES 3 , Gilles B RILLAT 3 1 GEEPS, Paris, France 2 Laboratoire Ampère, Lyon, France 3 LAPLACE, Toulouse, France 14/09/16 1 / 23

Outline Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion 2 / 23

Outline Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion 3 / 23

Advantages of die embedding The Printed-Circuit-Board technology (PCB) enables: ◮ higher interconnect density ◮ multi-layer ◮ small pitch (down to 25 µ m linewidth) ◮ Low inductance [1] ◮ small size ◮ laminated busbar structure ◮ batch-processed manufacturing E. Hoene, “Ultra Low Inductance Package for SiC” ECPE ◮ all interconnects are processed at once workshop on power boards, 2012, [1] 4 / 23

Advantages of die embedding The Printed-Circuit-Board technology (PCB) enables: ◮ higher interconnect density ◮ multi-layer ◮ small pitch (down to 25 µ m linewidth) ◮ Low inductance [1] ◮ small size ◮ laminated busbar structure ◮ batch-processed manufacturing E. Hoene, “Ultra Low Inductance Package for SiC” ECPE ◮ all interconnects are processed at once workshop on power boards, 2012, [1] 4 / 23

Advantages of die embedding The Printed-Circuit-Board technology (PCB) enables: ◮ higher interconnect density ◮ multi-layer ◮ small pitch (down to 25 µ m linewidth) ◮ Low inductance [1] ◮ small size ◮ laminated busbar structure ◮ batch-processed manufacturing E. Hoene, “Ultra Low Inductance Package for SiC” ECPE ◮ all interconnects are processed at once workshop on power boards, 2012, [1] 4 / 23

Literature Review – Die embedding in PCB – 1 Patents on chip embedding [2] A. Ostmann, “Leistungselektronik in der Leiterplatte” AT&S Technologieforum, 2013 ◮ Very active area in recent years ◮ Many applications to high interconnect density ◮ Several industrial developments (AT&S, Schweizer, etc.) 5 / 23

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Literature Review – Die embedding in PCB – 2 Low-inductance packaging for SiC [1] ◮ Half bridge module ◮ 0.8 nH loop inductance ◮ Embedding die using stud bumps E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power boards, 2012 [1] ◮ Power module development through german project Hi-LEVEL [3] ◮ 10 kW and 50 kW demonstrators ◮ Thick copper or DBC for thermal management ❤tt♣✿✴✴✇✇✇✳♣❝❞❛♥❞❢✳❝♦♠✴♣❝❞❡s✐❣♥✴✐♥❞❡①✳♣❤♣✴❡❞✐t♦r✐❛❧✴♠❡♥✉✲❢❡❛t✉r❡s✴✾✷✺✼✲❝♦♠♣♦♥❡♥t✲♣❛❝❦❛❣✐♥❣✲✶✹✵✺ 6 / 23

Outline Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion 7 / 23

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 8 / 23

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 8 / 23

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 8 / 23

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 8 / 23

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 8 / 23

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 8 / 23

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 8 / 23

Overview of the process – significant points ◮ Backside die attach with silver sintering: ◮ The die does not move during assembly ◮ Accurate positioning ◮ Ablation using a CO 2 laser ◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask ◮ Prototype-scale equipment used ◮ Can manufacture prototypes from 4x4 cm 2 up to 21x28 cm 2 ◮ Affordable, useful for process development. 9 / 23

Overview of the process – significant points ◮ Backside die attach with silver sintering: ◮ The die does not move during assembly ◮ Accurate positioning ◮ Ablation using a CO 2 laser ◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask ◮ Prototype-scale equipment used ◮ Can manufacture prototypes from 4x4 cm 2 up to 21x28 cm 2 ◮ Affordable, useful for process development. 9 / 23

Overview of the process – significant points ◮ Backside die attach with silver sintering: ◮ The die does not move during assembly ◮ Accurate positioning ◮ Ablation using a CO 2 laser ◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask ◮ Prototype-scale equipment used ◮ Can manufacture prototypes from 4x4 cm 2 up to 21x28 cm 2 ◮ Affordable, useful for process development. 9 / 23

Die Preparation — Lab-scale process ◮ Standard Al topside Unsuitable ◮ Ti/Cu PVD with a shadow mask (50/500 nm) ◮ Simple process for singulated dies 10 / 23

Die Preparation — Lab-scale process Mask ◮ Standard Al topside Unsuitable ◮ Ti/Cu PVD with a shadow mask (50/500 nm) ◮ Simple process for singulated dies 10 / 23

Die Preparation — Lab-scale process Die Mask ◮ Standard Al topside Unsuitable ◮ Ti/Cu PVD with a shadow mask (50/500 nm) ◮ Simple process for singulated dies 10 / 23

Die Preparation — Lab-scale process Die Mask PVD ◮ Standard Al topside Unsuitable ◮ Ti/Cu PVD with a shadow mask (50/500 nm) ◮ Simple process for singulated dies 10 / 23

Die Preparation — Lab-scale process Die Mask PVD ◮ Standard Al topside Unsuitable ◮ Ti/Cu PVD with a shadow mask (50/500 nm) ◮ Simple process for singulated dies 5 × 5 mm 2 IGBT die 10 / 23

Cross section ◮ Vertical walls in epoxy layers ◮ Good self-alignment ◮ No degradation of die topside metal due to CO 2 laser ◮ Die contact not yet perfect 11 / 23

Outline Introduction Proposed Embedding Technique Effect of Contact Area/Layout Summary and Conclusion 12 / 23

Effect of Contact Area/Layout R Topside copper Wells ◮ Thick topside copper foil (35 µ m) ◮ Thin electroplated copper (10 µ m) Die ◮ Many wells: ◮ More copper section on walls ◮ Large well(s): ◮ Thicker die contact metallization Copper foil Electroplated copper ◮ reduction of topside copper section Die fiber-resin composite Die topside métallization 13 / 23

Effect of Contact Area/Layout R Topside copper Wells ◮ Thick topside copper foil (35 µ m) ◮ Thin electroplated copper (10 µ m) Die ◮ Many wells: ◮ More copper section on walls ◮ Large well(s): ◮ Thicker die contact metallization Copper foil Electroplated copper ◮ reduction of topside copper section Die fiber-resin composite Die topside métallization 13 / 23

Effect of Contact Area/Layout R Topside copper Wells ◮ Thick topside copper foil (35 µ m) ◮ Thin electroplated copper (10 µ m) Die ◮ Many wells: ◮ More copper section on walls ◮ Large well(s): ◮ Thicker die contact metallization Copper foil Electroplated copper ◮ reduction of topside copper section Die fiber-resin composite Die topside métallization 13 / 23

Modelling R access R top R Topside copper Wells R wall R cont Die R Al R die V in ◮ Structure divided into 100 × 100 µ m cells ◮ 2-D current flow assumed ◮ Generation of a meshed circuit of resistors ◮ Solving using Modified Nodal Analysis. 14 / 23

Modelling — Results 1 mm 2 4 mm 2 9 mm 2 16 mm 2 4 mm 2 9 mm 2 9 mm 2 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Voltage [V] 15 / 23

Modelling — Results (2) # of Surface Resistance Resistance decreases with: (mm 2 ) contacts (m Ω ) ◮ Contact area 1 1 3.80 ◮ Contact distribution 1 4 2.16 1 9 1.55 ➜ Well spread contacts are more 1 16 1.32 efficient 4 4 1.40 ➜ split 4 mm 2 contact 4 9 1.26 comparable to single 16 mm 2 9 9 1.13 16 / 23