Combinational Circuits Bit Equality Acyclic Network Bit equal a - PDF document

Overview of Logic Design Fundamental Hardware Requirements ◼ Communication Computer Architecture: Logic Design ⚫ How to get values from one place to another ◼ Computation ◼ Storage CSci 2021: Machine Architecture and Organization March 20th-23rd, 2018 Bits are Our Friends ◼ Everything expressed in terms of values 0 and 1 Your instructor: Stephen McCamant ◼ Communication ⚫ Low or high voltage on wire Based on slides originally by: ◼ Computation Randy Bryant and Dave O’Hallaron ⚫ Compute Boolean functions ◼ Storage ⚫ Store bits of information – 1 – – 2 – CS:APP3e CS:APP3e 1 2 Digital Signals Computing with Logic Gates And Or Not 0 1 0 a a out a out out b b Voltage out = a && b out = a || b out = ! a ◼ Outputs are Boolean functions of inputs Time ◼ Respond continuously to changes in inputs ◼ Use voltage thresholds to extract discrete values from ⚫ With some, small delay continuous signal Rising Delay Falling Delay ◼ Simplest version: 1-bit signal a && b b ⚫ Either high range (1) or low range (0) ⚫ With guard range between them Voltage ◼ Not strongly affected by noise or low quality circuit elements a ⚫ Can make circuits simple, small, and fast – 3 – – 4 – Time CS:APP3e CS:APP3e 3 4 Combinational Circuits Bit Equality Acyclic Network Bit equal a HCL Expression eq bool eq = (a&&b)||(!a&&!b) Primary Primary Inputs Outputs b ◼ Generate 1 if a and b are equal Hardware Control Language (HCL) Acyclic Network of Logic Gates ◼ Very simple hardware description language ⚫ Boolean operations have syntax similar to C logical operations ◼ Continously responds to changes on primary inputs ◼ We’ll use it to describe control logic for processors ◼ Primary outputs become (after some delay) Boolean functions of primary inputs – 5 – – 6 – CS:APP3e CS:APP3e 5 6

Word Equality Bit-Level Multiplexor Word-Level Representation b 63 eq 63 B s Bit MUX Eq Bit equal HCL Expression = a 63 A b 62 eq 62 bool out = (s&&a)||(!s&&b) Bit equal b a 62 out HCL Representation a bool Eq = (A == B) Eq b 1 eq 1 Bit equal ◼ Control signal s ◼ 64-bit word size a 1 ◼ Data signals a and b b 0 eq 0 ◼ HCL representation Bit equal ◼ Output a when s=1, b when s=0 ⚫ Equality operation a 0 ⚫ Generates Boolean value – 7 – – 8 – CS:APP3e CS:APP3e 7 8 Word Multiplexor Exercise Break: 4-input Mux Word-Level Representation s s • Suppose we want to choose between 4 signals, D0, D1, D2, and D3, using two selector bits S0 and S1 B b 63 MUX Out out 63 A • Can you build this out of 2-input muxes? a 63 HCL Representation int Out = [ b 62 S0 s : A; out 62 1 : B; D0 a 62 S1 ]; MUX D1 ◼ Select input word A or B MUX depending on control signal s out ◼ HCL representation D2 ⚫ Case expression MUX b 0 D3 ⚫ Series of test : value pairs out 0 ⚫ Output value for first a 0 successful test – 9 – – 10 – CS:APP3e CS:APP3e 9 10 HCL Word-Level Examples Arithmetic Logic Unit Minimum of 3 Words ◼ Find minimum of three 0 1 2 3 int Min3 = [ input words A < B && A < C : A; C Y Y Y Y ◼ HCL case expression A A A A Min3 B < A && B < C : B; B MIN3 A A A A A L X + Y L X - Y L X & Y L X ^ Y 1 : C; ◼ Final case guarantees U U U U ]; match X X X X B OF B OF B OF B OF ZF ZF ZF ZF CF CF CF CF 4-Way Multiplexor s1 ◼ Combinational logic s0 ◼ Select one of 4 inputs ⚫ Continuously responding to inputs int Out4 = [ D0 based on two control !s1&&!s0: D0; ◼ Control signal selects function computed D1 bits MUX4 Out4 !s1 : D1; ⚫ Corresponding to 4 arithmetic/logical operations in Y86-64 D2 ◼ HCL case expression !s0 : D2; D3 ◼ Also computes values for condition codes 1 : D3; ◼ Simplify tests by ]; assuming sequential matching – 11 – – 12 – CS:APP3e CS:APP3e 11 12

Storing 1 Bit Storing 1 Bit (cont.) Bistable Element Bistable Element q q Q+ Q+ !q !q Q – Q – q = 0 or 1 q = 0 or 1 Stable 1 V1 1 1 1 1 0.9 0.9 0.9 0.9 V in = V 2 0.8 0.8 0.8 0.8 V 2 0.7 V 2 V 2 0.7 0.7 0.7 Vin V1 V1 V1 V2 V2 V2 0.6 0.6 0.6 0.6 0.5 0.5 0.5 0.5 0.4 0.4 0.4 0.4 Metastable 0.3 0.3 0.3 V in V in V in 0.3 V 1 V 1 V 1 0.2 0.2 0.2 0.2 0.1 0.1 0.1 0.1 Stable 0 0 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 – 13 – – 14 – 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Vin Vin CS:APP3e Vin CS:APP3e Vin 13 14 Physical Analogy Registers Stable 1 Structure 1 1 i 7 0.9 D o 7 Q+ 0.9 C 0.8 i 6 0.8 D o 6 Q+ C 0.7 Vin 0.7 V1 i 5 V2 D V2 o 5 0.6 Q+ 0.6 C i 4 0.5 0.5 D o 4 Q+ I O C 0.4 0.4 Metastable i 3 D o 3 0.3 Q+ 0.3 C i 2 0.2 D o 2 0.2 Q+ C 0.1 0.1 i 1 Stable 0 D o 1 Clock Q+ 0 C 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 i 0 D Vin o 0 Q+ Vin C Clock Metastable ◼ Stores word of data ⚫ Different from program registers seen in assembly code Stable left Stable right ◼ Collection of edge-triggered latches ◼ Loads input on rising edge of clock – 15 – – 20 – CS:APP3e CS:APP3e 15 20 Register Operation State Machine Example Comb. Logic 0 State = x State = y ◼ Accumulator Rising circuit Input = y Output = x   Output = y A clock ◼ Load or L 0 Out x y U accumulate on MUX each cycle In 1 Load Clock ◼ Stores data bits ◼ For most of time acts as barrier between input and output Clock ◼ As clock rises, loads input Load x 0 x 1 x 2 x 3 x 4 x 5 In Out x 0 x 0 +x 1 x 0 +x 1 +x 2 x 3 x 3 +x 4 x 3 +x 4 +x 5 – 21 – – 22 – CS:APP3e CS:APP3e 21 22

Random-Access Memory Register File Timing valA Reading A srcA valW valA 2 x Register ◼ Like combinational logic Read ports W Write port A dstW srcA file valB ◼ Output data generated based on Register B srcB x file input address valB ⚫ After some delay B srcB Clock 2 Writing ◼ Stores multiple words of memory ◼ Like register ⚫ Address input specifies which word to read or write ◼ Update only as clock rises ◼ Register file ⚫ Holds values of program registers 2 x y 2 ⚫ %rax , %rsp , etc. valW y Rising Register   valW ⚫ Register identifier serves as address W dstW clock Register file 2 W dstW file » ID 15 (0xF) implies no read or write performed ◼ Multiple Ports ⚫ Can read and/or write multiple words in one cycle Clock Clock » Each has separate address and data input/output – 23 – – 24 – CS:APP3e CS:APP3e 23 24 Hardware Control Language HCL Operations ◼ Very simple hardware description language ◼ Classify by type of value returned ◼ Can only express limited aspects of hardware operation Boolean Expressions ⚫ Parts we want to explore and modify ◼ Logic Operations Data Types ⚫ a && b , a || b , !a ◼ bool : Boolean ◼ Word Comparisons ⚫ a , b , c , … ⚫ A == B , A != B , A < B , A <= B , A >= B , A > B ◼ int : words ◼ Set Membership ⚫ A , B , C , … ⚫ A in { B, C, D } ⚫ Does not specify word size---bytes, 64- bit words, … » Same as A == B || A == C || A == D Statements Word Expressions ◼ bool a = bool-expr ; ◼ Case expressions ⚫ [ a : A; b : B; c : C ] ◼ int A = int-expr ; ⚫ Evaluate test expressions a , b , c , … in sequence ⚫ Return word expression A , B , C , … for first successful test – 25 – – 26 – CS:APP3e CS:APP3e 25 26 Summary Computation ◼ Performed by combinational logic ◼ Computes Boolean functions ◼ Continuously reacts to input changes Storage ◼ Registers ⚫ Hold single words ⚫ Loaded as clock rises ◼ Random-access memories ⚫ Hold multiple words ⚫ Possible multiple read or write ports ⚫ Read word when address input changes ⚫ Write word as clock rises – 27 – CS:APP3e 27