CENG3420 Lab 2-2: LC-3b Simulator Tinghuan Chen Department of - PowerPoint PPT Presentation

CENG3420 Lab 2-2: LC-3b Simulator Tinghuan Chen Department of Computer Science and Engineering The Chinese University of Hong Kong thchen@cse.cuhk.edu.hk Spring 2018 1 / 22

Overview Basis LC-3b Example: Count From 10 To 1 Tasks 2 / 22

The Slides are self-contained? NO! Do please refer to following two documents: ◮ LC-3b-ISA.pdf ◮ LC-3b-assembly.pdf 3 / 22

Notations DR ◮ Destination register LSHF(A,b) ◮ Shift A to the left by b bits ◮ If A = 1111 1111 1111 1111, b = 5 ◮ Then LSHF(A,b) = 1111 1111 1110 0000 MEM[addr] ◮ Word starting at the given memory address setcc() ◮ Set condition codes N, Z, P based on DR value SEXT(A) ◮ Sign-extend A to 16 bits ◮ If A = 11 0000, SEXT(A) = 1111 1111 1111 0000 4 / 22

LC-3b Example 2: Count from 10 to 1 count10.asm : count10.cod : .ORIG x3000 0x3000 LEA R0, TEN 0xE005 LDW R1, R0, #0 0x6200 START ADD R1, R1, #-1 0x127F BRZ DONE 0x0401 BR START 0x0FFD 0xF025 DONE TRAP x25 0x000A TEN .FILL x000A .END 5 / 22

LEA : Load Effective Address 0x3000 .ORIG x3000 0xE005 LEA R0, TEN 0x6200 LDW R1, R0, #0 0x127F START ADD R1, R1, #-1 0x0401 BRZ DONE 0x0FFD BR START 0xF025 DONE TRAP x25 0x000A TEN .FILL x000A .END ◮ 0xE005 → 1110 000 000000101 1. DR = PC + 2+ LSHF(SEXT(PCoffset9),1); 2. setcc(); 6 / 22

LDW : Load Word 0x3000 .ORIG x3000 0xE005 LEA R0, TEN 0x6200 LDW R1, R0, #0 0x127F START ADD R1, R1, #-1 0x0401 BRZ DONE 0x0FFD BR START 0xF025 DONE TRAP x25 0x000A TEN .FILL x000A .END ◮ 0x6200 → 0110 001 000 000000 1. DR = MEM[BaseR + LSHF(SEXT(offset6), 1)]; 2. setcc(); 7 / 22

ADD : Addition 0x3000 .ORIG x3000 0xE005 LEA R0, TEN 0x6200 LDW R1, R0, #0 0x127F START ADD R1, R1, #-1 0x0401 BRZ DONE 0x0FFD BR START 0xF025 DONE TRAP x25 0x000A TEN .FILL x000A .END ◮ 0x127F → 0001 001 001 1 11111 1. DR = SR1 + SEXT(imm5); 2. setcc(); 8 / 22

Sample: Codes of Addition 1. DR = SR1 + SEXT(imm5); 2. setcc(); 9 / 22

BR : Conditional Branch 0x3000 .ORIG x3000 0xE005 LEA R0, TEN 0x6200 LDW R1, R0, #0 0x127F START ADD R1, R1, #-1 0x0401 BRZ DONE 0x0FFD BR START 0xF025 DONE TRAP x25 0x000A TEN .FILL x000A .END ◮ 0x0401 → 0000 010 000000001 1. if (CURRENT_LATCHES.Z) then: 2. PC = PC + 2 + LSHF(SEXT(PCoffset9), 1); 10 / 22

BR : Conditional Branch 0x3000 .ORIG x3000 0xE005 LEA R0, TEN 0x6200 LDW R1, R0, #0 0x127F START ADD R1, R1, #-1 0x0401 BRZ DONE 0x0FFD BR START 0xF025 DONE TRAP x25 0x000A TEN .FILL x000A .END ◮ 0x0401 → 0000 111 111111101 1. if (CURRENT_LATCHS.N || CURRENT_LATCHES.Z || CURRENT_LATCHES.P) then: 2. PC = PC + 2 + LSHF(SEXT(PCoffset9), 1); 11 / 22

TRAP x25 : Halt 0x3000 .ORIG x3000 0xE005 LEA R0, TEN 0x6200 LDW R1, R0, #0 0x127F START ADD R1, R1, #-1 0x0401 BRZ DONE 0x0FFD BR START 0xF025 DONE TRAP x25 0x000A TEN .FILL x000A .END ◮ 0x0401 → 1111 0000 00100101 1. R7 = PC + 2; 2. PC = MEM[LSHF(ZEXT(trapvect8), 1)]; 12 / 22

Sample: Codes of TRAP x25 1. R7 = PC + 2; 2. PC = MEM[LSHF(ZEXT(trapvect8), 1)]; 13 / 22

Task 2: partVal() function ◮ Implement int partVal (int, int, int) ; ◮ Then TRAP instruction is completed; 14 / 22

Task 2: SEXT() & setCC() functions ◮ Implement int SEXT (int , int) ◮ Implement void setCC(int) ◮ Then ADD instruction is completed 15 / 22

Golden Result of Task 2: bench/testTask2-2.cod 1. run 1 Registers : Instruction Count : 1 PC : 0x3002 Instructions : CCs: N = 0 Z = 0 P = 1 Registers: 0: 0x0000 1: 0x0001 2: 0x0000 process_instruction()| curInstr = 0x1261 3: 0x0000 4: 0x0000 5: 0x0000 6: 0x0000 7: 0x0000 16 / 22

Golden Result of Task 2: bench/testTask2-2.cod 2. Go on run 1 Registers : Instruction Count : 2 PC : 0x3004 Instructions : CCs: N = 0 Z = 0 P = 1 Registers: 0: 0x0000 1: 0x0002 2: 0x0000 process_instruction()| curInstr = 0x1261 3: 0x0000 4: 0x0000 5: 0x0000 6: 0x0000 7: 0x0000 17 / 22

Task 3: Parse LEA, LDW, BR instructions ◮ Finish the following parts ◮ Please refer implementations of ADD, TRAP ◮ Then the simulator can work on count10.cod 18 / 22

Golden Result of Task 3: bench/count10.cod 1. run 2 Registers : Instruction Count : 2 Instructions : PC : 0x3004 CCs: N = 0 Z = 0 P = 1 Registers: 0: 0x300c 1: 0x000a process_instruction()| curInstr = 0xe005 2: 0x0000 process_instruction()| curInstr = 0x6200 3: 0x0000 4: 0x0000 5: 0x0000 6: 0x0000 7: 0x0000 19 / 22

Golden Result of Task 3: bench/count10.cod 2. Go on run 6 Registers : Instrustions : Instruction Count : 8 PC : 0x3004 CCs: N = 0 Z = 0 P = 1 Registers: process_instruction()| curInstr = 0x127f 0: 0x300c process_instruction()| curInstr = 0x0401 1: 0x0008 process_instruction()| curInstr = 0x0ffd 2: 0x0000 process_instruction()| curInstr = 0x127f 3: 0x0000 process_instruction()| curInstr = 0x0401 4: 0x0000 process_instruction()| curInstr = 0x0ffd 5: 0x0000 6: 0x0000 7: 0x0000 20 / 22

Golden Result of Task 3: bench/count10.cod 3. Go on run 12 Registers : Instrustions : Instruction Count : 20 process_instruction()| curInstr = 0x127f PC : 0x3004 process_instruction()| curInstr = 0x0401 CCs: N = 0 Z = 0 P = 1 process_instruction()| curInstr = 0x0ffd Registers: process_instruction()| curInstr = 0x127f 0: 0x300c process_instruction()| curInstr = 0x0401 1: 0x0004 process_instruction()| curInstr = 0x0ffd 2: 0x0000 process_instruction()| curInstr = 0x127f 3: 0x0000 process_instruction()| curInstr = 0x0401 4: 0x0000 process_instruction()| curInstr = 0x0ffd 5: 0x0000 process_instruction()| curInstr = 0x127f 6: 0x0000 process_instruction()| curInstr = 0x0401 7: 0x0000 process_instruction()| curInstr = 0x0ffd 21 / 22

Golden Result of Task 3: bench/count10.cod 4. Go on run 12 Registers : Instrustions : Instruction Count : 32 process_instruction()| curInstr = 0x127f PC : 0x0000 process_instruction()| curInstr = 0x0401 CCs: N = 0 Z = 1 P = 0 process_instruction()| curInstr = 0x0ffd Registers: process_instruction()| curInstr = 0x127f 0: 0x300c process_instruction()| curInstr = 0x0401 1: 0x0000 process_instruction()| curInstr = 0x0ffd 2: 0x0000 process_instruction()| curInstr = 0x127f 3: 0x0000 process_instruction()| curInstr = 0x0401 4: 0x0000 process_instruction()| curInstr = 0x0ffd 5: 0x0000 process_instruction()| curInstr = 0x127f 6: 0x0000 process_instruction()| curInstr = 0x0401 7: 0x300c process_instruction()| curInstr = 0xf025 22 / 22

CENG3420 Lab 2-2: LC-3b Simulator Tinghuan Chen Department of - PowerPoint PPT Presentation

CENG3420 Lab 2-2: LC-3b Simulator Tinghuan Chen Department of Computer Science and Engineering The Chinese University of Hong Kong thchen@cse.cuhk.edu.hk Spring 2018 1 / 22 Overview Basis LC-3b Example: Count From 10 To 1 Tasks 2 / 22

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