power driven dnn dataflow optimization on fpga
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Power-Driven DNN Dataflow Optimization on FPGA Qi Sun 1 , Tinghuan - PowerPoint PPT Presentation

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Power-Driven DNN Dataflow Optimization on FPGA Qi Sun 1 , Tinghuan Chen 1 , Jin Miao 2 , Bei Yu 1 1 The Chinese University of Hong Kong 2 Cadence Design Systems, Inc. 1 / 22 FPGA Targeted DNN Accelerator Design Flow Dataflow Synthesis HLS Model

  1. Power-Driven DNN Dataflow Optimization on FPGA Qi Sun 1 , Tinghuan Chen 1 , Jin Miao 2 , Bei Yu 1 1 The Chinese University of Hong Kong 2 Cadence Design Systems, Inc. 1 / 22

  2. FPGA Targeted DNN Accelerator Design Flow Dataflow Synthesis HLS Model DNN Model Design Space & Description Exploration Deployment FPGA Architecture Design ◮ Design power efficient dataflow with limited latency loss ◮ Enabled by proposed power modeling and a hierarchical strategy 2 / 22

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