Breakthrough Insight into DDR4/LPDDR4 Memory Greater Than 2400 Mb/s January 2015 Jennie Grosslight Product Manager
Agenda – Overview • Benefits and challenges for DDR4 and LPDDR4 >2400Mb/s • Breakthrough Insight Gained from Logic Analyzer – Techniques to address debug and validation challenges • DDR Eye Scan insight • DDR4 >3.1 Gb/s DIMM system - Tuning tool - Waveforms and Burst Trigger - View Initialization - Follow the initialization signal flow - Compliance and Performance Tools – Successful logic analyzer probing techniques for higher data rates – DDR Solution Overview, Recommendations, & Q&A Page 2
DDR4 and LPDDR4 Benefits DDR4 Benefits • Up to 30-40% power savings over DDR3 • More power control ( power savings and reliability improvement) • Targeting 3.2Gbps data rate …( possibly higher improves bandwidth) • Higher density (double # of banks) • More error checking (improves reliability) • Lower price than LPDDR3 (this will make DDR4 attractive to some mobile applications). LPDDR4 Benefits • Up to 40% power efficiency over DDR4 & greater than 40% over LPDDR3 in standby • LVSTL interface with VSSQ termination • Enables data rates over 3.2Gb/s • Increases bandwidth per pin • Single Data Rate CA signals = easier to maintain good signal integrity Page 3
DDR4 and LPDDR4 Design Challenges “How will I maximize the benefits?” • Faster data rates and smaller signal swings • Extreme space constraints • New protocols with new features require new memory controllers • Memory controllers must be smarter • Power management features need to be understood to optimize systems. • Risk that systems will not behave as designed Maintaining signal integrity at higher data rates with smaller signal swings is a significant challenge Page 4
Capturing DDR4 and LPDDR4 at Higher Data Rates DQ capture over 2400Mb/s is particularly challenging Data Rate (Mb/s) 4500 LPDDR4 4000 3500 2015 - DDR4 Majority 3000 new DDR3 designs 2500 2400 Mb/s will be in this 2000 range LPDDR3 1500 1000 500 0 2013 2014 2015 2016 Page 5
DDR4 and LPDDR4 Challenges Data Valid Windows Shrinking Data Rates Increasing Signal swing decreasing Read DDR4 Signal integrity variations between systems 3120 Read DDR4 Data Rate 2400 DDR4 3120, 2400 and 1600 eyes were less Read DDR4 1867 than 200mV at the DDR4 interposer! Read DDR4 1600 Data valid windows scanned on U4154B logic analyzers with FS2510 DDR4 DIMM interposer on different DDR4 targets. 2013 2015 Page 6
Breakthrough capture of DDR4 or LPDDR4 at highest data rates Proven DDR4 capture >3.1Gb/s Proven LPDDR4 capture at 3.2Gb/s U4154B system configuration for DDR4 DIMM capture over 2.5Gb/s: • 3 modules • M9505A chassis • M9536A embedded controller • FS2510 DDR4 DIMM Interposer (with FS1070 kit for DDR4 > 2.5Gb/s) U4154B system configurations vary for DDR2/3/4 and Page 7 LPDDR/2/3/4 technologies and probing use models.
Insight Gained from Logic Analyzer Timing modes – See when events happen • Asynchronous to system under test • High Resolution is most useful >2400Mb/s State mode – Follow signal flow – see what happened • Synchronous to clock from system • Enables most powerful SW tools DDR eye scan mode – eye diagrams • Unique qualified views of all ADD/CMD/DQ/DQS Page 8 Sept 18, 2012
Benefit: Highest Confidence in Measurement Accuracy Superior Insight into Bus Level Signal Integrity – Quickly view signals relative to each other • Complete view of address and data lines – Bus Level Signal Integrity Insight • Overlay mode • Signal Trace Mode – Capture data valid windows 100 ps by 100 mv Page 9
Validate and Debug DDR3/4 or LPDDR3/4 Powerful system for test and validation – High Resolution around trigger event • Timing Zoom – State Mode functional Validation • Synchronous to clock in system under test – Up to 200M deep traces • Industry deepest logic analyzer trace on DDR/LPDDR data State Waveforms Page 10
Achieve Greater Insight Faster Full Suite of Software Productivity Tools – Compliance Testing • DDR2/3/4 and LPDDR/2/3/4 – System Performance Analysis • DDR2/3/4 and LPDDR/2/3/4 – Real Time and Custom Violation Measurements • Memory and General Purpose Applications – DDR and LPDDR Decoder Tools State Waveforms • Protocol Decoding and Insight Page 11
Insight Gained from Logic Analyzer LPDDR4 - Speed Change Active 1 -2 sequence Clock turns on for 6 cycles before CKE enabled CA, BA, DQ, and DQS low unless driven high LPDDR4 Timing Zoom waveform – entering slower speed Page 12
Insight Gained from Logic Analyzer Follow the LPDDR4 signal flow Decoder output from State mode trace in listing view Data captured on rising and falling edges when over Active 1 -2 2.5Gb/s sequence Row and Column address decoded Data Burst of 16 Page 13
Agenda – Overview • Benefits and challenges for DDR4 and LPDDR4 >2400Mb/s • Breakthrough Insight Gained from Logic Analyzer – Techniques to address debug and validation challenges • DDR Eye Scan insight • DDR4 >3.1 Gb/s DIMM system - Tuning tool - Waveforms and Burst Trigger - View Initialization - Follow the initialization signal flow - Compliance and Performance Tools – Successful logic analyzer probing techniques for higher data rates – DDR Solution Overview, Recommendations, & Q&A Page 14
Challenge: Eye openings on DDR4 > 3.1Gb/s Eye Scan Insight: • Potential ODT setting issue. Threshold of first bit in burst has less swing than remainder of burst. • Could also be ISI (inter-symbol interference) • Overdriving DDR4 DRAM to 1.4V could cause damage. Next Steps: • Take trace to inspect ODT operation • Cross trigger scope to check for ISI Page 15
Challenge: System Signal Integrity DDR4 >3.1Gb/s DIMM system Eye Scan Insight: • DQS2 has less swing than other DQS Next Steps: • Check DQS DRAM drive strength, termination and trace routing Page 16
Challenge: Achieving Correct Signal Transitions Symptom: Data Corruption on DDR4 system Eye Scan Insight DDR4 Bank group 1 Transitioning incorrectly Next Steps: • SW work around: – Do not use BG1 = 1 – Limits address space • Long term: HW fix required Page 17
Challenge: Strobe Alignment Symptom: • Data corruption on LPDDR3 system Eye Scan Insights: • DQS2 & DQS3 not in alignment with DQS0 & DQS1 • DQS3 pre-amble is wrong, low to high instead of High to low. Eye Scan Settings: Burst Scan, No back-to-back Next Steps: • Check driver circuitry and SW Page January 2014
Challenge: Setting up measurements quickly Tuning tool – DDR Setup Assistant Used DDR setup assistant with 10 simple steps to setup State mode measurements Page 19
Challenge: Triggering on sequential events at high speeds DDR4 > 3.1Gbps Waveforms and Burst Trigger (TZ) in label designates Timing Zoom, High resolution Timing waveforms State waveforms - Rising & Falling edge samples DQ 7-0 Page 20
Challenge: Capturing initialization sequences Example: DDR4 >3.1Gb/s Initialization • 4M State Waveform, initialization sequence • Trigger stores only valid commands and enough samples after a Read or Write to capture data bursts. Page 21
Capturing System Initialization … continued Follow the initialization signal flow of DDR4 3.2Gb/s system Page 22
Challenge: Functional Compliance Testing Compliance and Performance Tools Compliance Tools • Post process • Real time Performance Analysis • Provides bus statistic information. • Provides histogram view on number of access at a specific memory address Page 23
Agenda – Overview • Benefits and challenges for DDR4 and LPDDR4 >2400Mb/s • Breakthrough Insight Gained from Logic Analyzer – Techniques to address debug and validation challenges • DDR Eye Scan insight • DDR4 >3.1 Gb/s DIMM system - Tuning tool - Waveforms and Burst Trigger - View Initialization - Follow the initialization signal flow - Compliance and Performance Tools – Successful logic analyzer probing techniques for higher data rates – DDR Solution Overview, Recommendations, & Q&A Page 24
Proven Probing Techniques to Capture Highest Data Rates Industry standard interposers = Designed and available! DDR4 DIMM interposer DDR4 SODIMM Interposer DDR4 x4/x8 BGA interposer User designs probing into system under test Specialty probing from Keysight Joint technical effort to meet specific needs Follow Design guidelines! Run simulations! Soft Touch Pro Mid-Bus Probing LPDDR3 POP interposer Page MemCon 25
DDR4 Interposers FS2510 Proven DDR4 >3.1Gb/s simultaneous Read and Write capture with FS1070 conversion kit Ease of connection Direct connect to U4154B FS2510: DDR4 DIMM interposer Low profile - Minimal loading Support UDIMM or RDIMM Timing and State analysis Support DDR Setup Assistant and DDR Eye Scan FS2512B: DDR4 1867 SODIMM interposer Page 26
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