Sig ignal In Integrity Checks Ba Babak Abi 30 August 2018 1 - PowerPoint PPT Presentation

DPM Status update Sig ignal In Integrity Checks Ba Babak Abi 30 August 2018 1

DPM Design simply includes : • ZYNQ: XCZU15EG-1FFVB1156E samtec M2 NMVe • DDR4 : MT40A1G16WBU-083(twin die) in two separate banks 1. 4x DDR4 (8 GB) connected to PL 2. 4x DDR4 (8 GB) connected to PS DDR4 PL • M.2 NMVe: 512 GB on DPM connected to PCIe Gen2 on top of ZYNQ DDR4s • Dimensions: 89 mm x 110 mm DDR4 PS • 24 GHT TX and 24 GTH RX connecte to 2 samtec connecter • PCB stack is 20 layers samtec • We would like to have review on signal integrity check particularly for the DDR4 delays. The GTH and PCie are pretty under control. • If anybody interested to do review we can provid the board’s Hyperlinx file, schematic, a ibis for ZYNQ and DDR4. ZYNQ’s pin flight-times in excel.

Address/Command/... 24 GTH @10GE 48 TX/RX 10GB/s termi U15 U14 U13 U12 natio PL DDR4 DDR4 DDR4 DDR4 n U7 DATA,DQ,DQS.. ZYNQ XCZU15EG PS PCIe Gen2 J6 connector termi U19 U18 U17 U16 natio DDR4 DDR4 DDR4 DDR4 n

PCB stack up 20 layers – no back drill samtec

PCB stack up 20 layers – no back drill 20 layers but still very busy board samtec

GTH lines Compliance: COM (10GBASE-KR) All passes 10GBASE-KR

GTH lines Compliance: plots1 • Insertion loss and Fitted attenuation are important

GTH lines Compliance: plots 2 • Some of near end RL are a bit higher the we like: even it is not important but we would like to fix them to reduce risk of failure due to impedance deviation in PCB manufacturing

Long Stub

VIA stubs 3D simulation Many simulation with different via structure is done to get the best via for each GTH line

SerDesResults_20180815-0200 Before C:\work\dpm_lmb_zynq_ultrascale_c01\Output\SerDesResults_20180817-0157 SerDesResults_20180817-0157 After

Before After

Before After

Backup

GTH lines Compliance COM (10GBASE-KR) bit sequences From file : DDR4_lineSIM_MEM_A4_ZYNQ_PL_MEM.ffs

TDR impedance TX0 Line

Overshooting through Dadd