Block Diagram of Level 1 Pattern Pixel Track Vertex Recognition - PowerPoint PPT Presentation

Block Diagram of Level 1 Pattern Pixel Track Vertex Recognition System Reconstruction Reconstruction FPGA DSP Associative Vertex Farm Memory (1 DSP per crossing) DSP Track Farm Average Average (4 DSPs per crossing) Latency: Latency: 0.4 µ s 250 µ s Average Latency: 200 µ s Average latency for the Level 1 trigger: 0.5 ms Number of DSPs (e.g. TMS320C6701): 1 1 2000 + 500 = 2500

BTeV Pixel Trigger (FPGA) -Form Hit Clusters, sort by quadrant (More Parallel) -Search “In out” and “Out in” in precision bend view -Start near pipe and near edge – Use Beam/Material constraints -Find Confirming hit, then match non-bend pixels Fake Hit -Pass on info to DSP’s Fake Inside Hole Plane Of Next plane Outside, but close, Approach reduces combinatorics too and from beam

BTeV Pixel Trigger (DSP Part A) DSP’s Form tracks form segments found by FPGA’s -BTeVGEANT contains hadronic Tracking 85% efficient > 5GeV interactions, γ conversions, δ -rays -Pixel hits have non-Gaussian tails (derived from test beam data) After clean up cuts -Average of 2 interactions per crossing Tracks get passed to Vertex DSP Momentum of tracks in fiducial

BTeV Pixel Trigger (DSP Part B) -Form Verticies -Require 2 tracks: 74% a) Within 2mm of primary b) > 6 “errors” of impact Keep ~50% of B’s 1% Reject 99% of min bias

L1 Trigger Performance State efficiency(%) state efficiency(%) B → π + π - 63 B o → K + π - 63 B s → D s K 71 B o → J/ ψ K s 50 B - → D o K - 70 B s → J/ ψ K * 68 B - → K s π - 27 B o → ρ o π o 56 � Full GEANT simulations including pattern recognition done for trigger Refinements and Recoveries in Level 2 and Level 3

Pixel hits after 1 st segment finding

This is the most Dramatic change..