Asynchronous logical networks II Digital Systems M 1
State variable coding impact on the behaviour ? Safe again…. With the last coding.. X 1 X 2 Y 1 Y 2 00 01 11 10 Z A 00 11 00 00 00 0 (Transition table NOT a Karnaugh map) B 11 11 10 00 00 0 The transition indicated by the red arrow is very C 10 00 10 01 00 0 dangerous. Theoretically from 10 (stable for input 01) with input 11 the state should switch to 01 (stable – dashed D 01 00 00 01 00 1 red arrow). But one of the two state variables necessarily X 1 X 2 switches before the other Y 1 00 01 11 10 In the case of the green arrow (10->00) Y1 is the first to Y 2 change and the system reaches the state 00 (wrong !) 00 11 00 00 00 0 which is stable with input 11 ! In the case of the blue arrow (10->11) where Y 2 switches first the system reaches the state 11 which for 11 input 11 11 10 00 00 0 shows a further race (once again a double state change from 11 to 00). If in this case Y 2 switches first the system 10 00 10 01 00 0 reaches the wanted state 01 (stable) with input 11 otherwise the system goes back to state 10 with a possible oscillation . Everything depends on the 01 00 00 01 00 1 combinatorial network delays A race is a state transition where two ore more state variables must switch concurrently A race is critical if a wrong stable state is reached because of non concurrent state variables change 2
Another (non primitive) state table N.B. this isn’t the safe Combined inputs-states effects X 2 X 1 X 2 X 1 00 01 11 10 00 01 11 10 Z Z Karnaugh Y 2 Y 1 Y 2 Y 1 A 00 D A C B A 00 11 00 10 01 0 0 0 B 01 B A A B B 01 01 00 00 01 0 0 0 blue -> transition Green -> race C 10 A C C C D 11 11 00 11 00 1 1 0 Red -> stable state D 11 D A D A C 10 00 10 10 10 0 1 This table (among other problems) has a critical race. A is stable with input 01. If the input should switch to 10 (double input change) the state to be reached should be B (black solid arrow). In practice there are two possibilities: either X 1 switches first or the other way round. If X 2 switches first the input transition indicated by the red arrow (00->10->10) occurs leading to to stable state C with 10 ! If X 1 switches first the blue transition occurs which in turn can lead to different situations if starting from state A-00 (with input 00 and theoretical destination D-11) either Y 1 or Y 2 switches first. In the first case it is possible that the wanted final state is reached (violet dashed transition). In the second case (dashed green transition) the system reaches C stable again! It must be noticed that further input or states delays could provoke even different dynamic transitions!! In this table we have supposed a double input change which must in any case be avoided 3
How to cope with this situation ? Setting aside the input problems let’s analyse all the races (green) of the state variables that is all transitions which imply the change of two state variables. The previous table can be modified. Multiple transitions . In circled orange the modifications X 2 X 1 00 01 11 10 Z Y 2 Y 1 In the first column from C the system Multiple A 00 11 00 10 01 0 10 should switch to A and then to D. It is Transition therefore possible to switch directly to D. B 01 01 00 00 01 0 By so doing a multiple transition from A(00) to D(11) (A->C->D) is possible. D 11 11 00 11 00 1 01 01 C 10 00 10 10 10 0 11 Future Multiple state Transition change Transition change Some remarks: • Multiple transitions are not always possible (more are the stables states in a column more unlikely are multiple transitions) • In the columns where only a stable state is present it is not necessary to insert multiple transitions provided no oscillations can occur • Multiple transitions induce network delays 4
Let’s consider the safe initial synthesis X 1 X 2 Here we have a race . y 1 y 2 00 01 11 10 Z Theoretically since there is only one stable state in the column 00 01 00 00 00 0 no problems should arise but if the variables switching times are different an oscillation is 01 01 11 00 00 0 always possible. Better a multiple transition (11->01->00) 11 00 11 10 00 0 10 00 00 10 00 1 Z = Y 1 !Y 2 t+ τ = (!x 1 x 2 y 2 + x 1 x 2 y 1 ) t Y 1 = y 1 t+ τ = (!x 1 !x 2 !y 1 + !x 1 x 2 y 2 ) t Y 2 = y 2 5
Analysis of this asynchronous sequential circuit (inputs X1,X2 , Reset and output Z) • Detect the state variables and their equations and using the algebra theorems simplify them indicating what theorems have been used • Detect the state transition table and its problems (if any) • Detect all possible malfunctions and provide a table solving them • Synthesize the initial transition table (after removing the possible races) using SR feedback 6
Y1 Y2 Leaving aside Reset Y1= !(!x1 !x2) (y1 + x1y2) = (x1+x2)(y1+ x1y2)= x1y1 + x1y2 + x2y1 + x1x2y2= = x1y1 + x1y2 + x2y1 Idempotence ! Y2 = !(!x2y1 + !(x1x2 + y2)) = !(!x2y1) (x1x2+y2)= (x2 +!y1) (x1x2+y2)= = x1x2 + x1x2!y1 + x2y2 + !y1y2= x1x2 + x2y2 + !y1y2 Z = y1!y2 7
A gate system is controlled by two pushbuttons X1 and X2. When closed the gate will be opened only after the sequence 10-00-01 is activated. Once open the gate will remain open until the closure sequence 11-01-11 is activated. Once closed the gate will remain closed and will be opened only when another open sequence is activated. Design the system with the Mealy model and a primitive state diagram. Once derived the state variables expressions implement the system in VHDL and by simulation check the correctness of your design inserting the correct and the wrong sequences. Use process and «if» structures in VHDL. X 1 X 2 ,Z 00,1 01,1 00,0 10,0 00,0 10,0 00,0 00,1 01,- L L C D B A 01,1 10,0 10,1 11,0 11,1 00,1 00,0 10,1 11,0 E F M H G 01,1 11,- 11,1 01,0 01,1 11,1 10,1 11,0 01,0 VHDL Bidirectional_lock
X 1 X 2 y 1 y 2 00 01 11 10 00 00 00 01 00 0 01 01 01 11 11 0 11 00 11 11 10 0 10 00 10 11 10 1 01 is never stable and reacheable (it can be reached only from state 00 with 11 input BUT is unstable) Y1= x1y1 + x1y2 + x2y1 Y2 = x1x2 + x2y2 + !y1y2 Z = y1!y2 9
X 1 X 2 y 1 y 2 00 01 11 10 00 00 00 01 00 0 01 01 01 11 11 0 In red the only critical race 11 00 11 11 10 0 10 00 10 11 10 1 X 1 X 2 y 1 y 2 00 01 11 10 00 00 00 01 00 0 01 01 01 11 11 0 Table without critical races 11 10 11 11 10 0 10 00 10 11 10 1 10
X 1 X 2 y 1 y 2 00 01 11 10 00 00 00 01 00 0 Simplified equivalent table (how must 01 - - 11 - 0 it be modified to insert a don’t care in the only transition leading to the 11 10 11 11 10 0 unstable state 01 ?) 10 00 10 11 10 1 Y 1 = y 2 + X 2 y 1 + X 1 y 1 Removed race Y 2 = X 2 y 2 + X 1 X 2 X 1 X 2 y 1 y 2 00 01 11 10 Initial table without critical race (zeros red/blue -> R=1 S=0 with 00 00 00 01 00 0 black zeros , ones red/blue -> S=1, 01 01 01 11 11 0 R=0 with black ones) S 1 = X 1 y 2 11 10 11 11 10 0 R 1 = !X 1 !X 2 !y 2 10 00 10 11 10 1 S 2 = X 1 X 2 R2 = !X 2 y 1 11
Incompletely specified state/transition tables X 1 X 2 y 1 y 2 00 01 11 10 Z 00 00 01 00 10 0 The green transitions can NEVER occur since two simultaneous inputs changes 01 00 01 11 11 0 can never occur ….. 11 00 01 11 10 0 10 00 00 11 10 1 X 1 X 2 y 1 y 2 00 01 11 10 Z … and therefore can be substituted with ”don’t care” 00 00 01 -- 10 0 Y 1 =X 1 01 00 01 11 -- 0 Y 2 =X 2 The network is combinatorial as it could 11 -- 01 11 10 0 be immediately detected (the stable states 10 00 -- 11 10 1 coincide with the inputs !!!). A table where each state is stable for only one input configuration is a primitive table 12
How is an asynchronous sequential network designed? - 1 1 st step: a primitive state diagram must be designed. If for each transition a new state is reached (or inserted) no problem, provided the history of the circuit is correctly interpreted otherwise the state number explodes. It must be understood the time development of the circuit and to detect the states which correct represent this develooment. There are no algorithms to design the state diagram but the human brain only Safe again X 1 X 2 ,Z 01,0 11,1 00,0 • Mealy (but could be Moore) 01 • The transitions outputs are don’t cares 01,0 11,- A B C since their values are not important (the 00,0 difference is only WHEN the change occurs) 10,- • Primitive table 01,- • From C with input 01 the transition is not 00,0 10,0 00,0 to B otherwise the output would be activated without the correct sequence (see 11,0 01,0 circuit history) D F E • The states D,E and F do not belong to the 10,0 11,0 correct sequence 10,0 11,0 01,0 13
How is an asynchronous sequential network designed? - 2 2 nd step: primitive state table (the transition which would imply the change of two inputs variables are don’t cares) X 1 X 2 ,Z 01,0 11,1 X 1 X 2 00,0 00 01 11 10 A,0 B,0 -,- A D,0 01,0 11,- A B C 00,0 A,0 B,0 C,- -,- B 10,- C -,- E,- C,1 D,- 01,- 00,0 10,0 00,0 A,0 -,- F,0 D,0 D 11,0 01,0 A,0 E,0 F,0 -,- E D F E 10,0 11,0 -,- E,0 F,0 D,0 F 10,0 11,0 01,0 14
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