An algorithmic Analog to Ditital Converter for CMOS image sensors Master’s Thesis Presentation Deyan Dimitrov Link¨ oping University June 12, 2013 Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
Outline Analog readout schemes in CMOS Image Sensors (CIS) General performance requirements from a column-parallel CIS ADC The Algorithmic/Cyclic ADC architecture A few explored MDAC configurations The Cyclic ADC implementation Designed ADC characterization and results Some improvement ideas Conclusion and possible future tasks Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
Introduction to image sensor readout R O W R O W D E C O D E R D E C O D E R Column Amplifiers/Sample and Hold to on-chip 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 processing Column Multiplexers ADC Local Memory and Drivers Basic serial readout Basic parallel readout Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
A pixel (the device under read) Main pixel parameters coupled to A photogate-based active pixel ADC requirements: VDD Output range Integration (exposure) time V reset PG TX Reset time n n p + Dark Noise V word out PSRR Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
Requirements over column-parallel CIS ADCs Integral Non-Linearity - random uniform (8-bit image) Random uniform INL distribution. 15 Random uniform INL distribution. 15 10 10 5 Dev in LSB 5 0 Dev in LSB 0 −5 −5 −10 −10 −15 0 50 100 150 200 250 Code −15 0 50 100 150 200 250 Code ± 1 LSB ± 8 LSB For visible spectrum, human eye starts recognizing distortion beyond 6-7% INL Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
Requirements over column-parallel CIS ADCs cont’d Differential Non-Linearity - random single missing codes over the whole range (up-to 1 code from stair-to-stair) Reference Image Random missing codes Even if ± 1 LSB, artifacts become visible to the eye. Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
Requirements over column-parallel CIS ADCs cont’d Column ADC mismatch fixed-pattern noise effect (8-bit image), pattern used ∆ rand 1 , ∆ rand 2 , ∆ rand 3 ... ± 2 LSB ± 16 LSB Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
Requirements over column-parallel CIS ADCs cont’d Full-scale step-response Out of range recovery Random noise Conversion speed: 1 τ pix res + τ pix sig Hf s (1) τ conv < ≈ − N me N me n cds 2 Power consumption, typically: 100 ÷ 500 µ W Resolution: 8 (very high speed imagers) ÷ 14 bits Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The Algorithmic/Cyclic ADC architecture Why cyclic? analog input iteration loop MDAC φ cycle φ in x2 vAnalogIn Sub-DA Sub-AD residual signal RSD [1 :0] digitized analog signal partial result RSD to BIN Logic WORDOUT [12 :0] A functional block diagram of a RSD Cyclic ADC Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The Algorithmic/Cyclic ADC architecture cont’d The RSD error correction scheme V out V out clipped output only offsets over 7 8 and below 1 8 will not be corrected V ref 3 4 V ref 1 4 V ref offset offset V in V in ”00” ”01” ”10” ”0” ”1” A comparative example between RSD and conventional ADC stages Allows for Sub-AD comparator online offset error correction during each consecutive iteration (cycle) Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
A few explored MDAC configurations The ”flip-around” MDAC Advantages/Disadvantages: architecture ⊕ Offset cancellation φ 2 ⊕ Parasitic insensitive φ 1 ⊖ Amplifier BW limited φ 1 C f ⊖ Matching dependent V in φ 1 V out C s φ 2 virtual ground V r (0 , ± V ref ) Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
A few explored MDAC configurations cont’d The ”modified flip-around” Advantages/Disadvantages: MDAC architecture ⊕ Non-OP-BW limited ( φ 1 ) φ 2 ⊕ Allows OP re-use at φ 1 φ 1 C f ⊖ No offset cancellation V in φ 1 ⊖ Matching dependent V out C s φ 1 φ 1 φ 2 V r (0 , ± V ref ) More popular than the previous due to OP BW independence Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
A few explored MDAC configurations cont’d The cap-stacking concept An SC integrator - multiply by n structure 2 V in V in V in C f V in φ 1 φ 2 q = CV in q = CV in C parasitic C s V out φ 1 φ 2 V in Opamp high gain requirement Accumulates offset Parasitic sensitive Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
A few explored MDAC configurations cont’d A MDAC with integrated analog CDS φ 3 φ 4 C 1 V ref + under-range C 3 to comparators C 3 C 1 C 2 C 2 C 3 V sig C 2 C 1 V reset C 4 C 5 V ref + C 5 C 6 to comparators C 6 V ref − V ref − C 5 C 4 within range C 4 C 6 over-range Signal sampling Reset sampling Feedback and amplification High complexity, non-trivial to design ”Bulky” design, multiple switches, phases, capacitors Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
Preliminary followed ADC design specifications Parameter Value Unit Resolution 12 bits Sampling rate > 130 kSps Integral Non-Linearity < 10 LSB Differential Non-Linearity < 0.5 LSB Power consumption < 300 µ W Supply voltage 3.3 ± 10% V Process node 0.18 µ m Area - µ m Main ADC specifications followed during the design study Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The implemented Cyclic ADC φ SD φ 1 D V IN φ INIT C 2 φ 0 φ S to comparators φ N C 1 a φ 2 V RH φ M φ 1 Vcom φ P C 1 b V RL Vcom Principal schematic diagram of the cyclic core-architecture, as proposed by Jong-Ho Park et. al. Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The implemented Cyclic ADC cont’d OTA requirements Possible candidates Telescopic OTA DC Gain: > 84 dB Current mirror OTA ω ug : > 10 MHz Folded cascode OTA PSRR: > 40 dB Two stage OTA Offset: ALAP Noise: < 200 µ V 2 at BW range Power: 30 ÷ 50 µ W Input and output ranges > pixel range Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The implemented Cyclic ADC cont’d VDD VDD VDD VDD B : 1 1 : B M 3 M 4 M 5 M 6 V bias V bias M 11 M 9 V IN n V IN p V out M 1 M 2 V bias C L V bias M 12 M 10 I bias M 7 M 8 The implemented current mirror OTA architecture Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The implemented Cyclic ADC cont’d Comparator requirements Explored candidates Input offset: Static latched comparator ± 1 8 ( V RH − V RL ) A Class AB latched Response time: < 500 ns comparator Resolution: > 400 µ V A fully dynamic latched comparator Noise variance: < Input offset Kickback noise: < left OTA recover time Power: < 10 µ W Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The implemented Cyclic ADC cont’d VDD VDD VDD VDD VDD VDD ′ ′ ′ ′ ′ ′ ′′ ′′ ′′ ′′ ′′ ′′ ′′′ ′′′ ′′′ ′′′ ′′′ ′′′ M M M M M M M M M M M M M M M M M M 10 8 5 6 9 11 10 8 5 6 9 11 10 8 5 6 9 11 V lat V lat V lat V lat V lat V lat V ONH V OP H V OP M V ONM V ONL V OP L ′ ′ ′′ ′′ ′′′ ′′′ M M M M M M 3 4 3 4 3 4 V PH V INp V PL V NL ′ ′ ′′ ′′ M M M M 1 2 1 2 V lat V lat ′ ′′ M M 7 7 A principal schematic diagram of the implemented Sub-AD comparators Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The implemented Cyclic ADC cont’d Switch requirements Explored candidates Input range: V RL ÷ V RH + Clock-boosted techniques margin A Bootstrapped switch R on : to achieve a reasonable technique settling-time A transmission-gate based Charge injection: at MSB switch cycle < V LSB distortion Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
The implemented Cyclic ADC cont’d LA φ SD φ 1 D ∆ V IN φ 1 φ INIT φ 1 D LA φ 2 C 2 ∆ φ 0 φ S to comparators φ N C 1 a φ 2 V RH LA V gp φ M φ 1 Vcom electrons φ P C 1 b V in V RL V out holes V gn Vcom A clarification of the considered accuracy-critical switch nodes Deyan Dimitrov Link¨ oping University An algorithmic Analog to Ditital Converter for CMOS image sensors
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