Advanced FinFET Process Technology M. Masahara National Institute - PowerPoint PPT Presentation

National Institute of Advanced Industrial Science and Technology Advanced FinFET Process Technology M. Masahara National Institute of AIST 1

National Institute of Advanced Industrial Science and Technology Contents 1. 1. Introduction Introduction • • Merits and Issues of FinFET Merits and Issues of FinFET 2. 2. Advanced FinFET Process Technology Advanced FinFET Process Technology • • Vth Tuning Vth Tuning • • Vth Variation Vth Variation 3. Summary 3. Summary 2

National Institute of Advanced Industrial Science and Technology Multi-Gate FinFETs D D G G S S 1 st FinFET Patent FinFET in 1980 from AIST  Proposed by AIST in 1980 (named “FinFET” by UCB in 1999)  Ultrathin and undoped channel and self-aligned double gate  Extremely high short channel effect (SCE) immunity 3

National Institute of Advanced Industrial Science and Technology DIBL Benchmark  FinFETs show the smallest DIBL (=highest SCE immunity) 4

National Institute of Advanced Industrial Science and Technology Issues for Advanced FinFET  However, several technological issues still exist… Variation Fin Formation D D Stress Eng. Vth Tuning G G (110) Channel S S Low Resistive Source/Drain C para Compact Model SOI or Bulk I/O, ESD 5

National Institute of Advanced Industrial Science and Technology Contents 1. Introduction • Merits and Issues of FinFET 2. Advanced FinFET Process Technology • Vth Tuning • Vth Variation 3. Summary 6

National Institute of Advanced Industrial Science and Technology V th for FinFETs 1 p + -Si (5.25eV) n + -Si (4.17eV) 0.8 V thDG(NMOS) , - V thDG(PMOS) (V) 0.6 0.4 0.4V(LSTP) 0.2V(LOP) 0.2 0 -0.2 4 4.2 4.4 4.6 4.8 5 5.2 5.4 4.6eV 4.75eV 4.9eV Gate Workfunction (eV) AIST, IEEE TED 2007  V th has a linear relationship with Gate Workfunction  For low V th , dual metal gate (dual WF) is needed 7

National Institute of Advanced Industrial Science and Technology I d -V g for Poly- and TiN-Gate FinFET n + poly-Si gate TiN-gate 10 -3 10 -3 PMOS NMOS PMOS NMOS 10 -4 10 -4 Drain Current, I d [ A ] Drain Current, I d [ A ] |V d | = 1 V |V d | = 1 V 10 -5 10 -5 0.05 V 0.05 V 10 -6 10 -6 10 -7 10 -7 10 -8 10 -8 10 -9 10 -9 10 -10 10 -10 L g = 21  m L g = 21  m 10 -11 10 -11 W eff =7.5  m W eff =17  m W eff =7.5  m W eff =17  m 10 -12 10 -12 -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 Gate Voltage, V g [ V ] Gate Voltage, V g [ V ] Symmetric Vth Asymmetric Vth  Almost symmetrical Vth’s (normally off) are obtained thanks to the midgap work function of TiN (4.75 eV) 8

National Institute of Advanced Industrial Science and Technology Dual Metal Gate Integration Integration of TiN and TaCN gate FinFETs General approach: “Deposition and etching” Etching residue TiN nMOS TaCN pMOS Ref. M.M.Hussain et al., ESSDERC2007, p.207 This work : “Metal Inter-diffusion” For PMOS  Mo(4.95 eV) For NMOS  Ta(4.25 eV)/Mo stack  Ta Inter-diffusion in Mo (No metal etching) 9

National Institute of Advanced Industrial Science and Technology Ta diffusion in Mo Back-side SIMS Ta layer Mo layer SiO 2 Ta ion count [arb. unit] 10 0 Ta O 2+ diffusion 10 -1 As 10 -2 Annealed depo. (700 o C 1 h) 10 -3 0 5 10 15 Depth [nm]  Ta diffuses in Mo and piles-up at Mo/SiO 2 interface after annealing  Thus WF for NMOS is determined by Ta (4.25eV) 10

National Institute of Advanced Industrial Science and Technology Features of Dual MG FinFETs Ta and SiO 2 HM SiO 2 HM etchback Patterning of etchback Mo and Ta/Mo gates in nMOS region in pMOS region No metal residue 11

National Institute of Advanced Industrial Science and Technology I-V for Mo and Ta/Mo FinFETs PMOS NMOS Ta (low WF) Mo (high WF) Mo (high WF) low gate WF by Ta diffusion AIST, IEEE EDL 2008  For NMOS, low V th can be achieved by Ta diffusion in Mo  For PMOS, low V th can be achieved by Mo  Off leakage  Negligible 12

National Institute of Advanced Industrial Science and Technology Four-Terminal FinFET 4T-FinFET = Independent DG FinFET V th control gate D D D D Drive gate G G G1 G1 G2 G2 S S S S DG separation log I d log I d +V g2 I on I on I off -V g2 I off V g1 V g1 V thDG V th(G1)  Vth for FinFET can be controlled flexibly and individually by separating the DG 13

National Institute of Advanced Industrial Science and Technology DG Separation CMP Process ＳＥＭ Image after CMP CMP Stopper G D D G1 G2 CMP S S FinFET Formation DG Separation by CMP Local Etch-back Process ＳＥＭ Image after LEB Stopper Fin Gate Gate1 Resist Fin Top Source BOX Drain sub Gate2 100nm DG Separation by LEB FinFET Formation and Side Wall Lithography 14

National Institute of Advanced Industrial Science and Technology Vth Tuning by Controlling Vg2 D D G1 G1 G2 G2 S S T si = 8.5-nm,  = 0.79 & T si = 13-nm,  = 0.66 & T si = 23-nm,  = 0.42 & T si = 43-nm,  = 0.24 & 0.8 350 S-Slope [ mV/decade ] 0.6 300 0.4 250 0.2 V th [ V ] 0 200 -0.2 150 -0.4 -0.6 100 -0.8 50 -1 -1.2 0 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 V g2 [ V ]  Vth can be tuned from LSTP to HP flexibly by selecting a proper Vg2 (The Second Gate) 15

National Institute of Advanced Industrial Science and Technology Contents 1. Introduction • Merits and Issues of FinFET 2. Advanced FinFET Process Technology • Vth Tuning • Vth Variation 3. Summary 16

National Institute of Advanced Industrial Science and Technology V th Variation for MG FinFETs Possible V th Variation Sources (2) (1) Gate Length ( L g ) (1) (2) Fin Thickness ( T Si ) D G (4) (5) (3) Oxide Thickness ( T ox ) (4) RDF S (5) Work Function WFV (  m ) (3)  FinFET variability sources were systematically analyzed 17

National Institute of Advanced Industrial Science and Technology Main Cause of Vth Variation Measured  V th  L G =6.7 nm (measured) L G Source L G = 100 nm Dimension T Fin = 40 nm  T Fin =2.9 nm (measured) T Fin Source Variation sources <V th >= 0.42 V  Negligible  T ox =0.032 nm (measured) T ox Source  m Source Main Cause 0 5 10 15 20 25 30 35  V th [mV] AIST, IEEE EDL 2010  Dimension variation sources are negligible  Main cause of the V th variation is the Workfunction Variation 18

National Institute of Advanced Industrial Science and Technology Workfunction Variation RIE Ideal SiO 2 SiO 2 S  1-Metal  1-Metal Si Si G D  2-Metal Uniformly Randomly aligned Metal aligned Metal Lower Higher WF variation WF variation  Rough etched side wall causes randomly aligned metal grain and thus higher WF variation  If side wall is flat, uniformly aligned metal grain and thus lower WF variation can be expected 19

National Institute of Advanced Industrial Science and Technology Nano-Wet Etching Process 5000 5000 Etchant ： 2.38% TMAH 2.38% TMAH 2.38% TMAH (Resist Developer) Etching Depth [ nm ] Etching Depth [ nm ] 50 o C 50 o C 4000 4000 (Tetramethylammonium hydroxide) (110) (110) 359 nm/min 359 nm/min CH 3 CH 3 + + 3000 3000 OH - OH - CH 3 CH 3 N N CH 3 CH 3 (100) (100) 214 nm/min 214 nm/min 2000 2000 CH 3 CH 3 1000 1000 <110> (111) (111) 9 nm/min 9 nm/min <111> 0 0 0 0 5 5 10 10 15 15 Etching time [ min ] Etching time [ min ] fin-mask Si-fin TMAH SOI BOX AIST, IEDM 2006  Extremely low ER of (111) in TMAH  Flat (111) side wall 20

National Institute of Advanced Industrial Science and Technology SEM and STEM images of FinFET AIST, VLSI Symp. 2010 20 nm Gate T ox Source Drain H fin = 45 nm Si-fin T Si = 12 nm  Min. L g = 20 nm, T Si = 17.8 nm, H Si = 45 nm  Nano-Wet-Etched FinFET  Undoped channel  T ox (CET) = 2.3 nm by C-V  Gate Stack : PVD-TiN/SiO 2 21

National Institute of Advanced Industrial Science and Technology Measured  V th for Nano-Wet-Etched FinFET AIST, VLSI Symp. 2010 40 35 30  V th [ mV ] 25 20 15 10 5 PVD-TiN Gate CET = 2. 3 nm 0 0 5 10 15 20 25 1/(WL) 1/2 [ mm -1 ]  A Vt was significantly lowered by flattening the side channel 22

National Institute of Advanced Industrial Science and Technology Avt Benchmark List of reported A Vt values Bulk-planar Ref. # Device Organi- Gate Stack Author. Reference FDSOI Structure zation 4 1 FDSOI Poly/SiO2 A.Cathignol ST ESSDERC2006 FinFET C. Fenouillet- 2 FDSOI TiN/HfO2 ST IEDM2007 Beranger 4 FDSOI Avt =  Vt (LW) 1/2 [mV-um] 3 NiSi/ Y.Morita Hitachi VLSI2008 (SOTB) 3 4 Bulk-planar Poly/SiON T.Tsunomura Selete VLSI2008 7 5 Bulk-planar MG/HK F.Arnaud ST IEDM2008 12 6 Bulk-planar MG/HK S.Hasegawa Toshiba IEDM2008 5 7 Bulk-planar s-Si/SiON H.Fukutome Fujitsu IEDM2009 2 6 3 8 Bulk-planar HK/MG M.Goto Toshiba VLSI2009 9 2 11 LSTP22nm 10 9 FinFET Mo/SiO2 T.Matsukawa AIST VLSI2009 15 10 Bulk-planar MG/HK F.Arnaud ST IEDM2009 8 14 L.A.Ragnarsso 1 1 11 Bulk-planar MG/HK IMEC IEDM2009 n 13 L.A.Ragnarsso LSTP15nm 12 Bulk-planar MG/HK IMEC IEDM2009 n 13 FDSOI MG/HK K.Cheng IBM IEDM2009 0 14 FinFET TiN/HfSiO T.Chiarella IMEC ESSDERC2009 0 1 2 3 4 15 FinFET TiN/SiO2 Y.Liu AIST VLSI2010 Tox [nm] T. Matsukawa, et al., (AIST.) SOI Conf, 2011, 7.1.  Obtained Avt meets 22-nm-node SRAM requirement  For 15nm and beyond, Avt should be further reduced 23