Additionneurs Ultra Basse Tension en Technologie SOI 0,13 - PowerPoint PPT Presentation

Additionneurs Ultra Basse Tension en Technologie SOI 0,13 µ Partiellement Désertée Jean Philippe Blanc, Hélène Lhermet, Marc Belleville CEA LETI Département Systèmes pour l’Information et la Santé 13/5/03 1

Outlines Introduction SOI Dtmos & Floating Body 1bit Adder Circuit architecture & testability Tests results Conclusion 13/5/03 2

Purpose of this study SOI 0.13 technology based on partially depleted transistors Evaluation of DTMOS performances for low voltage digital applications Design and simulation of a 32-bits adder at low voltage (0.25V to 0.5V) The adder-circuits studied use different transistor types : -> floating body or DTMOS -> high speed or low leakage 13/5/03 3

SOI DTMOS Dynamic Threshold MOS (DTMOS) : SOI transistor of which the threshold voltage is dynamically controlled by connecting the body to the gate. interests for very low power applications: improved Ion/Ioff ratio no history effect drawbacks : larger gate capacitance larger area Floating body DTMOS transistor transistor 13/5/03 4

Mix architecture of the 1-bit adder The architecture is a mix between conventional logic and transmission gates. 3 versions with low Vt MOS . floating bodies only . floating bodies and DTMOS . DTMOS only 1 version with high Vt MOS (DTMOS only) 13/5/03 5

Layouts and photograph of Adders Adder with DTMOS only Adder with FB and DTMOS Area : 170 mm 2 Area : 90 mm 2 S O I − H 9 S O I 1 − A ft e r C M P − M e t a l 1 A dd e r HSOI9 After CMP-metal1 13/5/03 6

General Overview of the Adder - Testability 0.25V 1.2V 1.2V R IPPLE - CARRY 32- BITS ADDER 13/5/03 7

Testability - Level shifters Adder input level shifter to shift the voltage from 1.2V to 0.4V Adder output level shifter to shift the supply 1.2V voltage from 0.4V to 0.4V 1.2V 1.2V 13/5/03 8

Adder functionality tests Test timing period : 300 ns Adder supply voltage : 1.2 V to 0.2 V Nmos Pmos 1.2V 0.5V 0.45V 0.4V 0.3V 0.25V 0.24V 0.23V high speed 0.2V -0.3V FUNCTIONAL 1 error 3 errors floating body / DTMOS high speed FUNCTIONAL 1 error floating body only high speed FUNCTIONAL 2 errors DTMOS only low leakage 0.3V -0.4V FUNC- 1 error 3 errors DTMOS only TIONAL Conclusion: Adders using high speed transistors are functionnal for supply voltages down to 0.25V Adders using low leakage transistors are functionnal for supply voltages down to 0.5V 13/5/03 9

Adders delay time measurements For supply voltages below0.5V (normal use of DTMOS), the DTMOS only adder is found to be faster than the other adders. The high speed circuit is faster than the low leakage circuit. 350 300 300 250 250 200 Tadd(ns) 200 Tadd(ns) TaddFb TaddHS TaddBc 150 150 TaddLL 100 100 50 50 0 0 0,25 0,3 0,4 0,5 0,6 0,8 1 1,2 0,25 0,3 0,4 0,6 0,8 1 1,2 Vdd(V) Vdd(V) 13/5/03 10

Adders standby current Standby current increases in the DTMOS circuit for supply voltages over 0.6V due to direct bias of body/source diodes . Source/body leakage 1 . 00 E − 004 I s t andb y ( A ) 1 . 00 E − 005 I s tdb y F b I s tdb y B c 1 . 00 E − 006 1 . 00 E − 007 0 . 25 0 . 3 0 . 4 0 . 6 0 . 8 1 1 . 2 V dd ( V ) 13/5/03 11

Conclusion Aim : To evaluate DTMOS performances for low voltage digital applications ☞ Comparison of SOI DTMOS and Floating Body implementations ☞ 32-bits adder Results : ☞ SOI can provide ulta low voltage operation with floating body transistors or DTMOS ☞ DTMOS can be used to reduce circuits delays at very low voltage ☞ Layout area may be increased by using DTMOS transistors ☞ Power consumption may be increased by using DTMOS transistors ☞ For medium and low voltages, DTMOS shall be introduced only on the most capacitive lines 13/5/03 12