ADC Non-linearity Wenqiang Gu Brookhaven National Laboratory 1 - PowerPoint PPT Presentation

Calibration of the ProtoDUNE ADC Non-linearity Wenqiang Gu Brookhaven National Laboratory 1

Outline • ProtoDUNE TPC readout electronics • ADC nonlinearity (NL) and other issues • Motivation and idea of the NL calibration • Validation with a Monte Carlo study • Summary and working plan 2

ProtoDUNE TPC readout electronics µBooNE: 14 mv/fC + 2.0 µs • Cold preamplifier • Gain: 4.7, 7.8, 14, or 25 mV/fC • Shaping time: 0.5, 1.0, 2.0, or 3.0 µs • Cold ADC (Analog to Digital Converter) • Continuous time & amplitude  discrete t & amp. • 12 bits: 4096 minimum steps in full range (1.2V) • 2 MHz sampling rate WIRE V. Radeka et al. Cold electronics for ‘Giant’ Liquid SIGNAL Argon Time Projection Chambers , 3 J. Phys. Conf. Ser. 308 (2011) 012021.

Readout scheme of ADC circuit • 12 bits /channel saved in FIFO buffer • 16 channels per ADC circuit e.g. 2048 = 100,000,000,000 Least significant bits (LSB) Most significant bits (MSB) CHN15 ADC15 D0 – D11 Input Buffer FE FIFO ASIC CHN0 ADC0 D0 – D11 RST Clock READ 200MHz Internal IDXM (100MHz) Pattern P1 ADC ASIC IDXL Generator IDL 2:1 RST MUX FPGA READ 2 Global bits (CLK1:CLK0) IDXM  00 or 11 : Control signals from IDXL internal logic IDL  01: ADC control signals directly from FPGA CLK1:CLK0 4

Readout scheme of ADC circuit • 16 channels split into two readout chains from FIFO CHN15 ADC15 D0 – D11 Input Buffer FE FIFO ASIC CHN0 ADC0 D0 – D11 RST Clock READ 200MHz Internal IDXM (100MHz) Pattern P1 ADC ASIC IDXL Generator IDL 2:1 RST MUX FPGA READ 2 Global bits (CLK1:CLK0) IDXM  00 or 11 : Control signals from IDXL internal logic IDL  01: ADC control signals directly from FPGA CLK1:CLK0 5

Readout scheme of ADC circuit • The read/write logic must be synchronized through five control signals CHN15 ADC15 D0 – D11 Input Buffer FE FIFO ASIC CHN0 ADC0 D0 – D11 RST Clock READ 200MHz Internal IDXM (100MHz) Pattern P1 ADC ASIC IDXL Generator IDL 2:1 RST MUX FPGA READ 2 Global bits (CLK1:CLK0) IDXM  00 or 11 : Control signals from IDXL internal logic IDL  01: ADC control signals directly from FPGA CLK1:CLK0 6

Readout scheme of ADC circuit • These five signals can be generated internally inside the ADC by a 200 MHz clock (2 MHz digitization) or taken externally CHN15 ADC15 D0 – D11 Input Buffer FE FIFO ASIC CHN0 ADC0 D0 – D11 RST Clock READ 200MHz Internal IDXM (100MHz) Pattern P1 ADC ASIC IDXL Generator IDL 2:1 RST MUX FPGA READ 2 Global bits (CLK1:CLK0) IDXM  00 or 11 : Control signals from IDXL internal logic IDL  01: ADC control signals directly from FPGA CLK1:CLK0 7

Known issues for current ProtoDUNE ADC • Non-linearity (NL) • Stuck bits • Some bits lost randomly in a wire waveform stuck bit at 0 e.g. 101,001 ⇒ 000,000 or 111,111 noise • Can be mitigated by identifying them and interpolating the non-linearity waveform stuck bit at 63 • Low temperature degrades the electronics and read/write logics 8

Known issues for current ProtoDUNE ADC • Non-linearity (NL) • Stuck bits • Some bits lost randomly in a wire waveform e.g. 101,001 ⇒ 000,000 or 111,111 • Can be mitigated by identifying them and interpolating the waveform • External clock eases both issues • NL is sensitive to clock settings 9

Motivation of the NL calibration • 600e - ENC (equivalent noise charge) at ProtoDUNE • Given 14 mV/fC (preamp) and 0.3 mV/ADC conversion • 600 e - ≈ 0.1 fC ≈ 1.4 mV ≈ 4.5 ADCs • Would like to control the NL below 4 ADC for ADC true -ADC measure in the useful range By Hucheng 10

Difficulty from a bench test to ProtoDUNE Also, NL is sensitive to clock settings • Bench test • (bench test) clock is tuned for each ADC CALIBRATION SIGNAL • (protoDUNE) one clock shared by (KNOWN VOLTAGE) four ADC curcuits • ProtoDUNE No direct voltage input! WIRE SIGNAL 11

C. Adams et al., Ionization Electron Signal Processing in Single Phase LArTPCs II. Data/Simulation Comparison and Performance in MicroBooNE arXiv:1804.02583 Idea of the NL calibration setup Preamplifier ADC V(t) Pulser ηδ (t) 𝜊 : gain A(t) f NL : non-linearity R(t) : response • Similar setup as in MicroBooNE Caveat: cold environment also changes the response • 6 bit pulser, i.e. 64 programmable amplitudes (<1.4V) • four adjustable gains of preamplifier • R ( t ) : electronics response of preamplifier • f NL : non-linearity from ADC true to ADC measure 12

Effective sampling rate • 0.5 μ s sampling (2 MHz) • shift t 0 => effectively higher sampling rate 13

Direct measurement of non-linearity? A MC simulatoin ADC measure ADC true • Given a precise prediction of the preamp response  a direct measurement • However, low temperature change the response significantly 14

Naïve idea of the impact from NL • Assuming pulse voltage A(t) V(t) and the preamp gain do NOT change the shape 𝜃𝐻 : 64*4 𝜃𝐻 : 64*4 of response pulse voltage … … & preamp gain • NL distorts the shape t t × 1/ 𝜃𝐻 × 1/ 𝜃𝐻 differently for high ADC A(t) V(t) and low ADC with NL w/o NL 15 t t

Sanity check with a MC simulation w/o NL ADC measure ADC true All waveforms match perfectly × 1/ 𝜃𝐻 with NL Input NL in MC 16

Calibration strategy • By assuming a function of non-linearity NL varies among channels • a piecewise function • or a polynomial function • Minimize the variance in A(t)/ 𝜃 G • i.e. the effective response function • ~O(10k) data points & ~O(10) unknowns  should be a solvable problem • A channel by channel calibration plan 17

Proof of principle with MC simulation Amp input Pluse input Amp output saturation C (~185fF) saturation Δ V pin62 CSA V DAC : 0 ~ 1.2V Chn_N 63 steps SHAPER Preamp output voltage Gain: 4.7, 7.8, 14, 25 mV/fC ADC measure 9900 points ADC measure / (V DAC × G amp ) 10 MHz effective sample rate ADC true Pulse voltage • By ignoring some saturations in preamp, a 10k data set is possible 18

ADC measure ( 𝐵 𝑗 , 𝐻 𝑗 , 𝑢 𝑙 ) 𝜓 2 minimization 𝐻 𝑗 = pulse voltage × preamp gain (A normalization of charge input) index of the 𝛽 -th iteration 2 𝜓 2(𝛽) = ෍ 𝐵 𝑗 + 𝑔 𝛽 𝐵 𝑗 − 𝑆 𝛽−1 𝑢 𝑙 𝐻 𝑗 𝑗 Time tick for 𝐵 𝑗 𝑂 σ 𝐵 𝑗 +𝑔 (𝛽−1) (𝐵 𝑗 ) 1 𝑆 𝛽−1 (𝑢 𝑙 ) = is the 𝐻 𝑗 i -th data point effective response function NL correction function (Calculated with the NL function from best fit of previous iteration) (To be fitted out) 19

χ 2 minimization (cont ’) 𝑧 0 + 𝑧 1 − 𝑧 0 𝐵 𝑗 − 0 , 𝐵 𝑗 ∈ [0,1000) 1000 𝑧 1 + 𝑧 2 − 𝑧 1 𝐵 𝑗 − 1000 , 𝐵 𝑗 ∈ [1000,2000) 1000 For a piecewise function, 𝑔 𝐵 𝑗 = 𝑧 2 + 𝑧 3 − 𝑧 2 𝐵 𝑗 − 2000 , 𝐵 𝑗 ∈ [2000,3000) the coefficients are calculated 1000 𝑧 3 + 𝑧 4 − 𝑧 3 before the minimization 𝐵 𝑗 − 3000 , 𝐵 𝑗 ∈ [3000,4000) 1000 𝑔(𝐵 𝑗 ) = 𝑐 0 𝑧 0 + 𝑐 1 𝑧 1 + 𝑐 2 𝑧 2 + 𝑐 3 𝑧 3 + 𝑐 4 𝑧 4 y 5 y 3 y 4 y 1 y 2 𝐵 𝑗 𝐵 𝑗 b others = 0 𝑐 0 = 1 − 1000 , 𝑐 1 = 1000 , 𝐵 𝑗 ∈ [0,1000) 𝑐 1 = 1 − 𝐵 𝑗 −1000 1000 , 𝑐 2 = 𝐵 𝑗 −1000 1000 , 𝐵 𝑗 ∈ [1000,2000) 0 1000 3000 2000 4000 𝐵 𝑗 = 𝑐 2 = 1 − 𝐵 𝑗 −2000 1000 , 𝑐 3 = 𝐵 𝑗 −2000 1000 , 𝐵 𝑗 ∈ [2000,3000) 𝑐 3 = 1 − 𝐵 𝑗 −3000 1000 , 𝑐 4 = 𝐵 𝑗 −3000 1000 , 𝐵 𝑗 ∈ [3000,4000) 20

χ 2 minimization (cont ’) • Given 𝑔 𝐵 𝑗 from last iteration ( 𝛽 -1 th) or initial guess (0-th), an effective response function 𝑆(𝑢 𝑙 ) is obtained e.g., 𝑔 𝐵 𝑗 = 𝑐 0 𝑧 0 + 𝑐1𝑧 1 + ⋯ + 𝑐 4 𝑧 4 (five points)  𝜓 2 = σ 𝐵 𝑗 + 𝑐 0 𝑧 0 + ⋯ + 𝑐 4 𝑧 4 − 𝑆(𝑢 𝑙 )𝐻 𝑗 2 2 𝑧 0 𝑗 𝑗 𝑗 𝑗 𝑗 𝐵 𝑗 −𝑆𝐻 𝑗 −𝑐 0 −𝑐 1 −𝑐 2 −𝑐 3 −𝑐 4 = 𝑁 − 𝑆 ⋅ 𝑇 2 𝑧 1 = 𝐵 𝑛 −𝑆𝐻 𝑛 − … … … … … … 𝑧 2 𝑧 3 𝑧 4 ⇒ By minimizing 𝜓 2 , { 𝑧 0 , 𝑧 1 , 𝑧 2 , 𝑧 3 , 𝑧 4 } ≡ 𝑇 = 𝑆 𝑈 𝑆 −1 𝑆 𝑈 𝑁 ⇒ Iterate the minimization until 𝑔 𝐵 𝑗 converges 21

Evolution of the “best - fit” 𝑔(𝐵 𝑗 ) and 𝑆(𝑢) • Given initial value { 𝑧 𝑗 } = {0, 0, 0, 0, 0} • After several times of iterations, “best - fit” NL 𝑔(𝐵 𝑗 ) and effective response 𝑆(𝑢) tends to be stable • The spread in 𝑆(𝑢) significantly shrinks after minimization ADC true – ADC measure Iter. #1 𝑆(𝑢) Iter. #2 NL bias? Electronics True response Initial bias ≈ 9 True ADC measure 22

For initial values { 𝑧 𝑗 } = { 𝑧 true } • Not surprising. Ture 𝑔(𝐵 𝑗 ) and 𝑆(𝑢) are obtained given the initial values close to the true values 𝜓 2 = 5E-5 (iter# 5) 23

For initial values { 𝑧 𝑗 } = {-10, -10,-10,-10,-10} • The spread in 𝑆 𝑢 𝑙 is barely seen after iterations of 𝜓 2 minimization • Smaller biases in both 𝑔 𝐵 𝑗 and 𝑆(𝑢 𝑙 ) than { 𝑧 𝑗 } ={0, 0, 0, 0, 0} • Will the bias be a problem? (next slide) Δ =3.5 𝜓 2 = 0.0016 (iter# 5) Initial 24