A META MODEL SUPPORTING BOTH HARDWARE AND SMALLTALK-BASED EXECUTION - PowerPoint PPT Presentation

A META MODEL SUPPORTING BOTH HARDWARE AND SMALLTALK-BASED EXECUTION OF FPGA CIRCUITS Le Xuan Sang 1,2 Loïc Lagadec 1 , Luc Fabress 2 , Jannik Laval 2 and Noury Bouraqadi 2 1 Lab-STICC, ENSTA Bretagne 2 Institut Mines-Telecom, Mines Douai

ABOUT ME • LE Xuan Sang Application • 2014-2017 PHD student Application • Coupling FPGA / Smalltalk Synthesis Abstraction in robotic applications Processor FPGA 2

DESCRIPTION OF A CIRCUIT USING VHDL Interface -- libraries declararion library IEEE; use IEEE.STD_LOGIC_1164. ALL ; opcode use IEEE.NUMERIC_STD. ALL ; -- Entity declaration entity SimpleALU is A port ( R clk: in std_logic; ALU A,B: in std_logic_vector(31 downto 0); opcode: in std_logic; R: out std_logic_vector(31 downto 0) B ); end SimpleALU; clk -- Architecture architecture arch of SimpleALU is Signal r1,r2,r3:signed(31 downto 0) :=( others =>'0'); begin r1<=signed(A); r2<=signed(B); R<=std_logic_vector(r3); process (clk) begin if rising_edge(clk) then case opcode is when '0' => r3<=(r1+r2); when '1' => r3<= r1 AND r2; when others => ( others =>'0'); end case ; end if ; end process ; end architecture ; 3

DESCRIPTION OF A CIRCUIT USING VHDL Interface -- libraries declararion library IEEE; use IEEE.STD_LOGIC_1164. ALL ; opcode use IEEE.NUMERIC_STD. ALL ; -- Entity declaration entity SimpleALU is A port ( R clk: in std_logic; ALU A,B: in std_logic_vector(31 downto 0); opcode: in std_logic; R: out std_logic_vector(31 downto 0) B ); end SimpleALU; clk -- Architecture architecture arch of SimpleALU is Signal r1,r2,r3:signed(31 downto 0) :=( others =>'0'); begin r1<=signed(A); Components r2<=signed(B); R<=std_logic_vector(r3); • Operated in parallel process (clk) begin if rising_edge(clk) then • Activated when its inputs change case opcode is when '0' => r3<=(r1+r2); when '1' => r3<= r1 AND r2; when others => ( others =>'0'); • Signals assignment alway need a end case ; end if ; propagation delay to take effect end process ; end architecture ; 3

FPGA CIRCUIT MODELLING 3 problems 1 opcode (1) The meta-model must capture alu := SimpleALU new . A alu A:20. both the structure and the alu B:15. R ALU alu opcode: false . "add" behaviour of the circuit alu execute. alu R asInteger "35" B (2) The parallel characteristics + clk FPGA available ? propagation delay of the FPGA No Yes circuits must be taken into Simulated execution 3 on VM account 2 Execute on FPGA (3) Transparent execution of the Outputs circuit on FPGA 4

FULL SOLUTION VHDL Low level synthesis S y n t h L e S s i D s V r H t e l o E i D x p 0110 p o L m o r l t s o e C r Bit file r e s I MetaModel s n r FPGA r e t a e t P p r F f a a F L d c I VHDL D A e H Legacy V FX2Interface r o S t i a m l u VCD 5

FULL SOLUTION VHDL Low level synthesis S y n t h L e S s i D s V r H t e l o E i D x p 0110 p o L m o r l t s o e C r Bit file r e s I MetaModel s n r FPGA r e t a e t P p r F f a a F L d c I VHDL D A e H Legacy V FX2Interface r o S t i a m l u VCD 5

FULL SOLUTION VHDL Low level synthesis S y n t h L e S s i D s V r H t e l o E i D x p 0110 p o L m o r l t s o e C r Bit file r e s I MetaModel s n r FPGA r e t a e t P p r F f a a F L d c I VHDL D A e H Legacy V FX2Interface r o S t i a m l u VCD 5

FULL SOLUTION VHDL Low level synthesis S y n t h L e S s i D s V r H t e l o E i D x p 0110 p o L m o r l t s o e C r Bit file r e s I MetaModel s n r FPGA r e t a e t P p r F f a a F L d c I VHDL D A e H Legacy V FX2Interface r o S t i a m l u VCD 5

FULL SOLUTION VHDL Low level synthesis S y n t h L e S s i D s V r H t e l o E i D x p 0110 p o L m o r l t s o e C r Bit file r e s I MetaModel s n r FPGA r e t a e t P p r F f a a F L d c I VHDL D A e H Legacy V FX2Interface r o S t i a m l u VCD 5

FULL SOLUTION VHDL Low level synthesis S y n t h L e S s i D s V r H t e l o E i D x p 0110 p o L m o r l t s o e C r Bit file r e s I MetaModel s n r FPGA r e t a e t P p r F f a a F L d c I VHDL D A e H Legacy V FX2Interface r o S t i a m l u VCD 5

SMALLTALK-BASED EXECUTION OF THE FPGA CIRCUIT MODEL

EVENT-DRIVEN FOR PROPAGATION EXECUTION • All parallel components are considered as processes with sensitivity list (event listener) Start • The value of signals is changed only after Update signals value update Determine events occur • Events occur on signals change Execute processes triggered by events • All processes that have changed signals as inputs will become active End • Execution of a triggered process may trigger other processes 6

CIRCUIT MODEL EXECUTION • Inputs ports are assigned at the first time • Each circuit has a done signal alu := SimpleALU new. alu A :20. • The circuit is triggered by the clock alu B :15. alu opcode: false . clk alu execute. • The execution is repeated until the done signal is asserted 7

HARDWARE-BASED EXECUTION OF THE FPGA CIRCUIT MODEL

AUTOMATIC DEPLOYEMENT ON FPGA Final circuit 1. Generate automatically the communication interface SimpleALU A B R opcode 2. The VHDL codes is exported Interface from the model Export VHDL HW. configuration 3. The hardware configuration is generated 0110 4. The vendor tool-chain is used Bit file for low level synthesis Low level synthesis Program No effort for developper FPGA 8

HARDWARE BASED EXECUTION OF CIRCUIT MODEL 1. The inputs signals are assigned 2. The input values are encode as Pharo VM ByteArray and sent to FPGA 3. The interface circuit decodes the #[<A>,<B>,<opcode>] #[<R>] data it received and sends to the target circuit Interface A B opcode R 4. The outputs of the circuit can be SimpleALU fetched from Smalltalk in a reverse way 9

CONTROLLABILITY AND DEBUGGING

POST-MORTEM ANALYSIS OF SIMULATION • The circuit is executed for a alu := SimpleALU new. queue := { specific amount of time #clk clock: 50ns. #A change:{1. 3. 5. 7} every:50ns. #B change:{0. 2. 4. 6} every:50ns. #opcode change:{'0'.'1'} every:100ns. • The inputs are changed at } asTimeQueueFor:400ns. stream := WaveFormStream on:'ALU.vcd'. some specific points of alu modellingExecution:#execute timeQueue:queue dumpOn:stream. time • Next input changes are stored in a time queue • Timing information and signals values are traced continuously into a VCD file 10

HARDWARE BREAKPOINT • How can we manually stop the execution of FPGA circuit ? • Enables the software like debug capabilities on hardware 11

HARDWARE BREAKPOINT • How can we manually stop the global clock execution of FPGA circuit ? Target Clock clk • Enables the software like debug circuit controller capabilities on hardware 11

HARDWARE BREAKPOINT • How can we manually stop the global clock execution of FPGA circuit ? Target Clock clk • Enables the software like debug circuit controller capabilities on hardware 11

STATIC BREAKPOINT A simple counter …… SimpleCounter >>execute <hdl:#combinational> { self clk. self reset. self start} onChange: [ self reset = '1' ifTrue:[ cnt reset:'0'. ] ifFalse:[ self start = '1' ifTrue:[ cnt reset:'0'. done <- false . ] ifFalse:[ cnt = 100 ifTrue:[ done <- true . ] ifFalse:[ cnt <- (cnt +1).] cnt = 4 ifTrue:[ Halting self halt. ] ] ] ] dout <- cnt. 12

STATIC BREAKPOINT A simple counter global clock …… SimpleCounter >>execute Clock clock <hdl:#combinational> controller counter { self clk. self reset. self start} onChange: [ self reset = '1' ifTrue:[ clk cnt reset:'0'. halt done ] ifFalse:[ start Target self start = '1' ifTrue:[ circuit cnt reset:'0'. done <- false . ] ifFalse:[ cnt = 100 ifTrue:[ Inputs Output done <- true . Interface ] ifFalse:[ cnt <- (cnt +1).] cnt = 4 ifTrue:[ Halting self halt. ] ] ] ] • Need to re-synthesize the circuit dout <- cnt. when changing 12

DYNAMIC BREAKPOINT obj := SimpleCounter new. obj setBreakpointOn:#dout value:4. obj enableBreakpointOn:#dout. obj execute. "stop at breakpoint” “set another breakpoint” obj setBreakpointOn:#dout value:10. obj resume. "resume the execution” “stop when out = 10” obj resume. "Continue” 13

CONCLUSION AND FUTURE WORK • Future work VHDL Low level • Short term synthesis S y n t h L e S s i D s V r H t e l E o i D x p 0110 p L o m o • Extend the meta-model r l t o s e C r Bit file r e s I MetaModel s n r FPGA r e t • support software- a e t P p r F f a a F L d c I VHDL D A e hardware co-simulation H Legacy V FX2Interface r o S t i a m l u • Long term VCD • Get closer to Smalltalk : Smalltalk → FPGA 14