A Low Power Asynchronous GPS Baseband Processor Benjamin Z. Tang, - PowerPoint PPT Presentation

A Low Power Asynchronous GPS Baseband Processor Benjamin Z. Tang, Stephen Longfield, Jr., Sunil A. Bhave, Rajit Manohar Cornell University  Benjamin Tang 05/07/2012 - 1/18

Motivation Augmented reality Micro robotics navigation Location-based services Need continuous 1980s 1990s 2000s 2010s FUTURE operation, much Decreasing power, but still too high lower power  Benjamin Tang 05/07/2012 - 2/18

How Does GPS Work? • GPS L1 civil signal  L1 carrier Satellite  Pseudorandom noise code τ 3 (PRN) • 1ms repeat period, 1.023MHz τ 1 Receiver • Unique for each satellite  Navigation data τ 2 L1 carrier GPS satellite PRN code transmitted signal Navigation data  Benjamin Tang 05/07/2012 - 3/18

How Does Receiver Know… • Which satellite’s signal was received?  Use CDMA • Where the satellite is?  Orbital information in navigation data • When was the signal transmitted?  Navigation data + PRN code phase L1 carrier GPS satellite PRN code transmitted signal Navigation data  Benjamin Tang 05/07/2012 - 4/18

GPS Receiver “Channel” Our focus GPS Baseband GPS Baseband Processing GPS Baseband Processing GPS Baseband Processing GPS Baseband Processing GPS RF GPS Baseband Measurements & Decoded Processing Digital Samples Frontend Processing Message Position calculation Medium Negligible More power-hungry power power ~20-100mW <10mW  Benjamin Tang 05/07/2012 - 5/18

GPS Baseband Processing • Correlation in CDMA Received  Generate signal replica Receiver-generated  Multiply and accumulate code replica Output once every 1ms Subsystems should run at their natural kHz frequencies to be power-efficient Digital Samples Controls Accumulators Tracking ~1.023MHz Signal Replica & “Correlators” ~6 MHz , “Channel” Measurements & Decoded Data Message Decode 1kHz –  Benjamin Tang 50Hz 05/07/2012 - 6/18

Baseband Processor Design Options Options Correlators Tracking Decode Option 1 Software Software Software Option 2 Hardware Software Software Option 3 Hardware Hardware Hardware Our implementation Typical synchronous design issue: What clocks to use? • Shared with front end oscillator crystal Asynchronous:  Optimized for one particular front end  Clock ratios, unnecessary power Each subsystem • Independent oscillator crystals only runs as fast  Optimizations less front end dependent as it needs to  Clock ratios  Processor clock >> sampling clock, unnecessary power  Benjamin Tang 05/07/2012 - 7/18

Asynchronous GPS Baseband Processor • 6 channels • Selected optimizations • QDI and bundled data Bundled-data Shared tracking loops QDI Tracking Digital Samples Digital Samples Controls Controls Accumulators Accumulators Tracking Signal Replica Signal Replica Buffer Asymmetric acquisition Measurements & Decoded Measurements & Decoded Data Data Message Message Decode Decode  Benjamin Tang 05/07/2012 - 8/18

Asymmetric Acquisition Full Acquisition (Other receivers) Asymmetric Acquisition (Our receiver) (+) Acquires: satellite ID, code phase (-) Acquires: code phase offset, the rest offset and Doppler frequency from software (-) FFT engine and memory or thousands (+) Use pre-existing correlators of correlators Full acquisition not needed often. Use asymmetric acquisition scheme. Reduced hardware, Reduced area, Reduced power Digital Samples Controls Accumulators Tracking Signal Replica Measurements & Decoded Data Message Decode  Benjamin Tang 05/07/2012 - 9/18

Accumulators • Operate at input frequency • 6 accumulators per channel • 3-bit inputs iteratively added to 16-bit sum • Only dump output once every 1ms • Higher order bits do not switch often DUMP IN 3 16 DUMP Bit=0 Bit=0 Bit=1 Reg 16 OUT 16  Benjamin Tang 05/07/2012 - 10/18

Accumulators • Standard 3-bit accumulator coupled with a 13-bit constant time counter • Concatenate results at DUMP IN IN 3 3 16 3 DUMP DUMP Reg Reg 16 3 a OUT 16 3 Carry {b,a} OUT out 16 MSB b Counter 13 • 4X Naïve 16-bit accumulator: ~40 μ W Counter-based accumulator: ~10 μ W less power  Benjamin Tang 05/07/2012 - 11/18

Tracking Loops • Tightly coupled feedback loops • Defer updates  Need to provide updates before the next data sample  Slow tracking loops, shared between all channels, saves power  Fast tracking loops, power hungry Tracking Digital Samples Digital Samples Controls Controls Accumulators Accumulators Tracking Signal Replica Signal Replica Buffer Measurements & Decoded Data Measurements & Decoded Data Message Message Decode Decode  Benjamin Tang 05/07/2012 - 12/18

Tracking Loops • Frequency Locked Loop (FLL), Phase Locked Loop (PLL) and Delay Locked Loop (DLL) • Computations involve vector magnitude, arctangent, multiplication and division operations. Simplify:  Fixed point arithmetic, bundled-data     Apply Taylor series small angle approximation:    1 tan  Apply modified version of Robertson approximation:        2 2 1 1 max , A I Q I Q Q I 4 4 Position error increases by ~1m on average  Benjamin Tang 05/07/2012 - 13/18

Receiver Performance Simulations • Transistor-level implementation of our system • Position accuracy simulation  60 seconds of signal from commercial GPS signal simulator  No added atmospheric, ionospheric and multipath errors 3D-RMS error <4m  Benjamin Tang 05/07/2012 - 14/18

Power Simulations SPICE simulation: Vdd=1V, T=25 o C, 90nm technology Acquisition ( μ W) Track ( μ W) Subsystems (6 Channels) (6 Channels) Code Generator 41.8 39.9 Carrier NCO 477.4 442.8 Correlators Code NCO 439.4 400.2 Accumulators 367.3 359.9 Tracking Loops 5.5 5.8 Data Decode 1.9 2.1 Controls, Support 240.3 239.1 Total 1.49mW 1.41mW 1.4mW during continuous tracking  Benjamin Tang 05/07/2012 - 15/18

Comparison • Other contemporary GPS receivers (SOCs with integrated RF front end and baseband processing) Name This work MediaTek ST 0.11 μ m 0.18 μ m Process 90nm Voltage (V) 1.0 1.2 1.6 Number of Channels 6 22 12 System Power (mW) 1.4 34.0 56.0 RF Power (mW) - 19.5 20.0 10X lower 3X lower power Baseband Power (mW) 1.4 14.5 36.0 power per channel Baseband Power/Channel (mW) 0.2 0.7 3.0 Comparable 3-D rms Error (m) 3.9 - 3.0 accuracy  MediaTek (J.-M. Wei, et al., ISSCC 2009)  STMicroelectronics (G. Gramegna, et al., JSSC 2006)  Benjamin Tang 05/07/2012 - 16/18

Conclusion • Transistor-level implementation of a low power asynchronous GPS baseband processor  Only runs as fast as it needs to • Selected optimizations:  Asymmetric acquisition  Counter-based accumulators  Shared bundled-data tracking loops 1.4mW 3D-RMS < 4ms  Benjamin Tang 05/07/2012 - 17/18

Acknowledgement • Dr. Paul Kintner • DARPA HI-MEMS • National Science Foundation  Benjamin Tang 05/07/2012 - 18/18

A Low Power Asynchronous GPS Baseband Processor Benjamin Z. Tang, Stephen Longfield, Jr., Sunil A. Bhave, Rajit Manohar Cornell University  Benjamin Tang