A Few Problems with Physical Addressing Main memory 0: 1: - PowerPoint PPT Presentation

A Few Problems with Physical Addressing Main memory 0: 1: Physical address 2: Virtual Memory 3: (PA) CPU 4: 4 5: Process Abstraction, Part 2: Private Address Space 6: 7: 8: ... M-1: Motivation : why not direct physical memory access? Address translation with pages Data Optimizing translation : translation lookaside buffer Extra benefits : sharing and protection Memory as a contiguous array of bytes is a lie! Why? 1 2 Solution: Virtual Memory (address indirection ) Virtual Addressing and Address Translation data Virtual address space Memory Management Unit translates virtual address to physical address Main memory Process 1 virtual 0: Physical memory CPU Chip 1: addresses 2: Virtual address Physical address virtual-to-physical 3: (VA) (PA) CPU MMU mapping 4: 4 4100 physical 5: Virtual address space 6: addresses 7: 8: ... Process n virtual M-1: addresses data Data Private virtual address space Single physical address space per process. managed by OS/hardware. Physical addresses are invisible to programs. 6 9

Design for a Slow Disk: Exploit Locality fixed-size, aligned pages Page-based Mapping page size = power of two Virtual Virtual Memory Address Space Address Space 0 0 Virtual Virtual Physical Physical Memory Page Page Address Space Address Space 0 0 0 0 Physical Physical Virtual Virtual Page Page Page Page 0 0 1 1 Physical Physical Virtual Virtual Page Page Page Page 1 1 2 2 … … Virtual Virtual Map virtual pages Page Page … … 3 3 onto physical pages. on disk Physical Physical Page Page 2 p - 1 2 p - 1 2 m - 1 2 m - 1 Virtual Virtual Page Page 2 v - 1 2 v - 1 2 n - 1 Some virtual pages do not fit! 2 n - 1 Where are they stored? Page Table Address Translation with a Page Table Physical pages array of page table entries (PTEs) (Physical memory) mapping virtual page to where it is stored VP 1 PP 0 Virtual address (VA) Page table Physical Page Number base register or disk address Valid Virtual page number (VPN) Virtual page offset (VPO) VP 2 (PTBR) PTE 0 0 null Base address VP 7 Page table 1 of current process's 1 page table Valid Physical page number (PPN) VP 4 PP 3 0 1 0 null 0 PTE 7 1 Swap space Virtual page mapped page table (Disk) to physical page? VP 3 Yes = Page Hit Physical page number (PPN) Physical page offset (PPO) Memory resident, VP 6 managed by HW (MMU), OS Physical addres s (PA) How many page tables are in the system? 17 18

Page Fault: exceptional control flow Page Hit: virtual page in memory Physical pages (Physical memory) Virtual Page Number Process accessed virtual address in a page that is not in physical memory. VP 1 PP 0 Physical Page Number or disk address Valid Process VP 2 PTE 0 0 null VP 7 User Code OS exception handler 1 PP 0 1 PP 1 VP 4 PP 3 0 On disk exception: page fault 1 PP 3 movl 0 null Load page 0 On disk into memory return PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 Returns to faulting instruction: movl is executed again ! 19 21 "Page out" Page Fault: 1. page not in memory Page Fault: 2. OS evicts another page. Physical pages Physical pages (Physical memory) (Physical memory) Virtual Page Number Virtual Page Number VP 1 PP 0 VP 1 PP 0 Physical Page Number Physical Page Number or disk address or disk address Valid Valid VP 2 VP 2 PTE 0 0 null PTE 0 0 null VP 7 VP 7 1 PP 0 0 On disk 1 PP 1 1 PP 1 VP 4 VP 4 PP 3 PP 3 0 On disk 0 On disk 1 PP 3 1 PP 3 0 null 0 null 0 On disk 0 On disk PTE 7 1 PP 2 PTE 7 1 PP 2 Swap space Swap space page table page table (Disk) (Disk) VP 3 VP 3 What now? VP 6 VP 6 OS handles fault VP 1 22 23

"Page in" Terminology Page Fault: 3. OS loads needed page. Physical pages (Physical memory) context switch Virtual Page Number VP 3 PP 0 Switch control between processes on the same CPU. Physical Page Number page in or disk address Valid VP 2 PTE 0 0 null Move page of virtual memory from disk to physical memory. swap VP 7 1 On disk page out 1 PP 1 VP 4 PP 3 Move page of virtual memory from physical memory to disk. 1 PP 0 thrash 1 PP 3 0 null Total working set size of processes is larger than physical memory. 0 On disk Most time is spent paging in and out instead of doing useful computation. PTE 7 1 PP 2 Swap space page table (Disk) (I find all these terms useful when talking to other computer scientists about my brain…) VP 3 Finally: VP 6 Re-execute faulting instruction. Page hit! VP 1 Useful for "real life" too. 24 25 Address Translation: Page Hit Address Translation: Page Fault Exception Page fault handler 4 2 2 CPU Chip CPU Chip Victim page PTEA PTEA 1 1 PTE 5 VA Cache/ VA PTE Cache/ CPU MMU CPU MMU 3 Disk Memory Memory 3 7 PA New page 4 6 Data 1) Processor sends virtual address to MMU 5 2-3) MMU fetches PTE from page table in cache/memory 1) Processor sends virtual address to MMU ( memory management unit ) 4) Valid bit is zero, so MMU triggers page fault exception 5) Handler identifies victim (and, if dirty, pages it out to disk) 2-3) MMU fetches PTE from page table in cache/memory 6) Handler pages in new page and updates PTE in memory 4) MMU sends physical address to cache/memory 7) Handler returns to original process, restarting faulting instruction 5) Cache/memory sends data word to processor 26 27

How fast is translation? TLB Hit How many physical memory accesses are required to complete one virtual memory access? CPU Chip TLB PTE 2 3 VPN Translation Lookaside Buffer (TLB) 1 VA PA CPU MMU Cache/ Small hardware cache in MMU just for page table entries 4 Memory e.g., 128 or 256 entries Much faster than a page table lookup in memory. Data 5 In the running for "un/classiest name of a thing in CS" A TLB hit eliminates a memory access 28 29 Simple Memory System Example (small) TLB Miss Addressing Simulate accessing these virtual addresses on the system: 0x03D4, 0x0B8F, 0x0020 14-bit virtual addresses CPU Chip TLB 12-bit physical address 4 Page size = 64 bytes 2 PTE VPN 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 3 VA PTEA CPU MMU Cache/ PA Memory VPN VPO 5 Virtual Page Offset Virtual Page Number Data 6 11 10 9 8 7 6 5 4 3 2 1 0 A TLB miss incurs an additional memory access (the PTE) PPN PPO Fortunately, TLB misses are rare. Does a TLB miss require disk access? Physical Page Number Physical Page Offset 30 31

Simple Memory System Page Table Simple Memory System TLB Only showing first 16 entries (out of 256 = 2 8 ) 16 entries 4-way associative virtual page #___ TLB index___ TLB tag ____ TLB Hit? __ Page Fault? __ physical page #: ____ TLB ignores page offset. Why? VPN PPN Valid VPN PPN Valid 00 28 1 08 13 1 TLB tag TLB index 01 – 0 09 17 1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 02 33 1 0A 09 1 03 02 1 0B – 0 virtual page number virtual page offset 04 – 0 0C – 0 virtual page #___ TLB index___ TLB tag ____ TLB Hit? __ Page Fault? __ physical page #: ____ 05 16 1 0D 2D 1 06 – 0 0E 11 1 Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid 07 – 0 0F 0D 1 0 03 – 0 09 0D 1 00 – 0 07 02 1 1 03 2D 1 02 – 0 04 – 0 0A – 0 What about a real address space? Read more in the book… 2 02 – 0 08 – 0 06 – 0 03 – 0 3 07 – 0 03 0D 1 0A 34 1 02 – 0 32 33 Simple Memory System Cache 16 lines cache tag cache index cache offset 11 10 9 8 7 6 5 4 3 2 1 0 4-byte block size Physically addressed physical page number physical page offset Direct mapped cache offset___ cache index___ cache tag____ Hit? __ Byte: ____ Idx Tag Valid B0 B1 B2 B3 Idx Tag Valid B0 B1 B2 B3 0 19 1 99 11 23 11 8 24 1 3A 00 51 89 1 15 0 – – – – 9 2D 0 – – – – 2 1B 1 00 02 04 08 A 2D 1 93 15 DA 3B 3 36 0 – – – – B 0B 0 – – – – 4 32 1 43 6D 8F 09 C 12 0 – – – – 5 0D 1 36 72 F0 1D D 16 1 04 96 34 15 6 31 0 – – – – E 13 1 83 77 1B D3 7 16 1 11 C2 DF 03 F 14 0 – – – – 34