If you plot strain versus stress, it would be a linear relationship till elastic limit. Subsequently, the material undergoes plastic deformation and the strain decreases less rapidly with stress. The slope of the curve in the linear region is the Young’s modulus, Y, with units same as stress. Strain is a unit less quantity. 90
We had discussed previously that oversized or under sized substitutional dopants can create local stress. You can appreciate that the stress would result in stretched or compressed bonds which may be easier to break. When there are too many of them around, the stress may relax by migration of the point defects. In the 1D case shown, the defects can line up and form a line defect. Since there is local order with lesser stress along the line defect compared to the point defects, the former would be preferred. You may appreciate that when the point defects are far apart, i.e. when the concentration is low, the chances of such migration of point defects resulting in line defects would be smaller. 91
Other examples include deposition of Si3N4 on Silicon. Si3N4 typically has tensile stress. However the stress can be engineered by proper processing. Some kind of stress, either compressive or tensile is unavoidable. Let us say the nitride has a tensile stress. The underlying silicon would be under compressive stress. The stress may relax by formation of defects. For this reason, Si3N4 is typically not deposited directly on silicon. Another example is growth of crystalline Germanium on crystalline Silicon. The lattice constants are different for the two materials (Ge – 5.65 A, Si – 5.43 A) and hence the growth of Ge on top would result in tensile stress in the underlying Si. Typically this is relaxed by creation of defects at the interface between the two materials. Stress below elastic limit can also be used for mobility improvements in Si. Compressive stress in Si result in higher mobility of holes, whereas tensile stress would result in higher mobility of electrons. 92
Dislocations can also arise from a missing line of atoms or an extra line of Si atoms. Migration of interstitials and voids can also lead to such defects. Dislocations can introduce local disturbances in the period potential in the lattice, leading to distortion of the energy band structure. These distortions can create trap centers that would trap electrons and holes, leading to lowering of life time of carriers. Since dislocations extend over space, they can create leakage paths in junctions. The distortion in the band structure also would result in higher scattering of carriers in the vicinity of dislocations and this would reduce mobility. In processing, dislocations can result in enhanced local diffusion. 93
Dislocations can move in the crystal. For example the climb move can happen by loss of an atom from the end of the line. The dislocation can glide to the right by a rearrangement of atoms. During the growth of the ingots for manufacturing, such defects can be introduced. They can be grown out of the crystal by appropriate processing. 94
Electronic properties of stacking faults are similar to those of dislocations. 95
The left bottom image is a HRTEM (high-resolution TEM) image that shows the atomic structure of planar defects in thin-film silicon: an intrinsic stacking fault (ISF —in which adjacent layers are shifted slightly), and an extrinsic stacking fault (ESF —in which there is an intervening layer between two layers slightly shifted from each other). Text and images from: http://www.ece.umn.edu/groups/nsfret/TEMpics.html. NSF research experience for teachers program – 2005. Image on the top right is from Electron microscopy group, Department of Materials Science and Metallurgy, University of Cambridge. (GaN) 96
Silicon nanowires in this case were grown by vapor − liquid − solid (VLS) mechanism. 97
The image is a HRTEM (high-resolution TEM) image that shows the atomic structure of planar defects in thin-film silicon: a twin defect (in which the upper layers are rotated 180º from the lower layers. Text and images from: http://www.ece.umn.edu/groups/nsfret/TEMpics.html. NSF research experience for teachers program – 2005. 98
Examples of precipitates include dopant precipitates and complexes in Si doped beyond the solid solubility limit of the dopant, SiO2 precipitates in Czochralski Method. 99
We are now ready to look at Si wafer manufacturing for VLSI, other electronic devices like power devices and detectors, and solar cells. The wafer requirements are different for different applications. For VLSI applications, the devices are made within the top couple of micrometers of the wafer. The rest of the thickness of the wafer provides mechanical strength and stability during manufacturing. So wafers where the defects are kept away from the device regions during manufacturing and operation is acceptable. We would also look at silicon on insulator (SOI) wafers where the device is made on a thin layer of Si which is dielectrically isolated from the mechanical support. On the other hand for some of the power electronic devices, the device extends over the entire wafer thickness. Also some of the devices with high ampere rating could be the entire wafer (both thickness and area). In such cases defects should be completely avoided in wafers used for such applications. A higher degree of refinement is desirable in such cases with a disproportionate increase in cost. Disproportionate because the technologies are expensive and the volumes are low as these are niche applications. But since these are niche applications, customers may be ready to pay. For solar cell applications also the device is the entire wafer. There are additional constraints on the wafers for solar cell applications from cost and performance considerations. The cost is the cost of electricity produced, which include the cost of the wafer, cost of processing including the fab – people – consumables, ….., the land where you deploy the solar panels, maintenance, cost of funds (interest), etc. Higher efficiency can mean lower area for the same power generated. Which would mean lower land cost. But if the cost of cells with high efficiency is very high, we may settle for lower efficiency. Very high efficiency cells (25% world record cells on Si) are made on FZ wafers, commercial cells have efficiency in the range of 16%. The quality of the wafers for 16% is significantly lower than for 25%. 100
The first point is foremost important for solar cell applications. Suppose Si is an exhaustible resource. Large scale use of Silicon based solar cells for energy generation would then become uneconomical. Silicon is most commonly found in SiO2, which is the main component of sand. VLSI grade Si should have low impurity concentrations as we had seen in earlier lectures. However higher content of oxygen and carbon may be tolerated for VLSI applications. We would see the source of both these later. Circular versus square wafers. 101
Metallurgical grade wafers could be available 10 th of the cost of VLSI grade wafers. Refined or upgraded metallurgical grade (UMG) Si is currently being explored for solar cell applications due to potential reduction in cost. 102
The poly Si rods of EGS is used as the feedstock for single crystal growth. The rods can be used as such for float zone technique. The rods are crushed to pieces for Czochralski technique. 103
Further purification of the material is possible during crystal growth. This is achieved because the solubility of dopants or impurities in the liquid phase and solid phase are different. 104
Czochralski method for single crystal ingot manufacturing is shown on this slide. The pieces of electronic grade poly crystalline silicon are melted along with dopants. Typically pieces of heavily doped silicon is used for doping. The temperature would be maintained marginally above 1417C (melting point of Si). A seed of single crystal of desired orientation is then inserted into the melt. Pull the seed out slowly. Usually the crucible assembly and the seed are rotated, and rotated in opposite directions to stir the melt well. This keeps the melt uniformly heated with a uniform distribution of dopants. Crystalline silicon grows on the seed lattice plane by lattice plane. The rate of rotation and pull speed should be well controlled. Otherwise shear stresses on the growing planes would result in formation of dislocations and stacking faults. The quartz crucible would soften at such high temperature. So a mechanical support is required, which is provided by the graphite crucible. SiO2 from the quartz crucible would dissolve in the melt and oxygen would thus be incorporated into the growing crystal. The concentration of oxygen thus incorporated is in the range of 1E17 to 1E18 cm-3. The graphite would also evaporate and would be incorporated in the melt resulting an eventual concentration of 1E15 to 1E16 cm-3 in the crystal. Growth is usually carried out in Ar ambient to avoid other impurities from air. When the seed is inserted into the melt, large temperature gradients would exist between the seed and the melt resulting in generation of dislocations and stacking faults in the grown film. 105
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