28nm 8nm FDSOI DSOI Dig igit ital Desi esign Tut utorial orial MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble ‐ France
Con Context & Motiv tivation tion Develop a digital design flow, based on standard methodologies and CAD tools Detail each step of the digital flow: from RTL to GDSII Verilog RTL Plug an play tutorial (scripts and testbenches are delivered) Provide a typical digital example (synchronous, sequential) Propose the flow on an advanced CMOS technology: 28nm FDSOI GDSII layout First version (1.4) sent in June 2015 to 166 institutions Design ‐ Kit: CMOS28FDSOI 10ML, PDK 2.5.d A new tutorial release is planned for Q1/Q2 2016 Design ‐ Kit: CMOS28FDSOI 10ML, PDK 2.5.f New functionalities: body biasing, LVS and DRC verifications, etc… 2 CMP annual users meeting, 4 Feb. 2016, PARIS
RTL to RT to GDS GDS flo flow F Verilog RTL Test ‐ bench R CAD tools used in the tutorial are: O Cadence Incisiv (NCSim) N RC or DC RC or DC RTL RTL Synthesis Synthesis simulation simulation T Synopsys Design Compiler (DC) E Cadence RTL Compiler (RC) N Gate ‐ level SDF timing Test ‐ bench D Verilog netlist annotation Cadence Encounter (EDI) Cadence Virtuoso, version 6.1.6 EDI Place & EDI Place & Gate ‐ level Gate ‐ level Mentor Graphics Calibre Route Route simulation simulation B A C GDSII Physical Verilog SDF timing back ‐ Test ‐ bench K netlist annotation layout E N D Back annotated Back annotated Calibre Calibre Calibre Calibre simulation simulation DRC DRC LVS LVS LVS: Layout Versus Schematic DRC: Design Rules Checking 3 CMP annual users meeting, 4 Feb. 2016, PARIS
FIR FIR cir circuit uit exa example circuit called “TOP_FIR” TOP_FIR clk clk out[15:0] reset FIR_0 out[15:0] load eq reset in[15:0] eqc eq clk load reset load out[15:0] in[15:0] in[15 :0] clk 16 FIR reset FIR_15 out[15:0] load filters in in[15:0] parallel FIR: Finite Impulse Response Simulation results: Coefficients loading Outputs calculation Reset CMP annual users meeting, 4 Feb. 2016, PARIS
Logic sy Logic synt nthesis Synthesis Verilog RTL Gate level netlist RTL Compiler (Cadence) or Design Compiler (Synopsys) + Gate level simulation Gate level simulation Reset, loading and Testbench processing modes 5 CMP annual users meeting, 4 Feb. 2016, PARIS
Place Place and and ro route IOs placement Place and route Gate level netlist (+ top cell “PAD_TOP_FIR”) Floorplan generation Encounter Digital Power ‐ plan Implementation EDI Core cells placement (Cadence) GDSII layout Verilog netlist Clock tree synthesis Power routing Final routing SDF (timing generation) Verilog netlist and GDS STA (back ‐ annotation) SDF: Standard Delay Format 6 STA: Static Timing Analysis CMP annual users meeting, 4 Feb. 2016, PARIS
Sp Specific ific fe features in in 28nm 28nm FDSO FDSOI Meet particular DRC/ERC rules: WellTaps on all rows • (50µm spacing) Filler cells on top and bottom core rows • (OPC rules) Restricting the tool to use the 8 first metal layers to route signals, and the 2 top layers for power. Body biasing functionalities (detailed in next slide) DRC: Design Rules Checking ERC: Electrical Rules Checking 7 OPC: Optical Proximity Correcting CMP annual users meeting, 4 Feb. 2016, PARIS
Body Body bi biasi asing met methodol odology ogy flo flow Body biasing on LVT (flip ‐ well) transistors: Body bias Body bias FBB or RBB: speed or leakage optimization Body biasing in layout view: VDD VDDS Filler tap cell with separated power and ground rails : VDD/VDDS and GND/GNDS GNDS GND FBB: Forward Body Biasing 8 RBB: Reverse Body Biasing CMP annual users meeting, 4 Feb. 2016, PARIS
Body Body bi biasi asing met methodol odology ogy flo flow 4) Power stripes filler cells External VDDS and GNDS voltages to core cells: 1) External VDDS/GNDS I/O pads Specific library supporting FBB and RBB ( ‐ 1,8V to +1,8V supply voltage) 2) IO pads dedicated power rings VDDS VDDS GNDS GNDS 3) Power rings power stripes Fillers row GNDS VDDS Each row of functional cells is supplied FBB: Forward Body Biasing 9 RBB: Reverse Body Biasing CMP annual users meeting, 4 Feb. 2016, PARIS
Final Final ve verificat cations GDSII and netlist imported under Cadence Virtuoso: as layout and schematic views LVS and DRC verifications (on Calibre from Mentor Graphics or PVS from Cadence) When LVS and DRC succeed, the “TOP_FIR” circuit could be manufactured…! • DRC: Design Rules Checking 10 LVS: Layout Versus Schematic CMP annual users meeting, 4 Feb. 2016, PARIS
Tutorial deliv Tu livery 166 institutions received in June 2015 a first version of the tutorial A new tutorial release is planned for Q1/Q2 2016, integrating new functionalities: body biasing (forward and reverse • body biasing), LVS and DRC verifications, • wire bonding pads, • SRAM block • Already positive feedback from several designers ! Expected more digital designs in future MPW runs… DRC: Design Rules Checking LVS: Layout Versus Schematic 11 MPW: Multi ‐ Project Wafers CMP annual users meeting, 4 Feb. 2016, PARIS
Thank Thank yo you!
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