7/15/2014 Low Power Multicore Architecture Using FDSOI Technology Marcello Coppola STMicroelectronics Agenda 2 • FDSOI • STNOC with FDSOI • Application example • Conclusions 1
7/15/2014 FD-SOI Speed & Energy Efficiency June 2014 4 Faster, Cooler, Simpler Mature process & Enhanced design options technology ecosystem • FD-SOI transistors up to 30% • Back-biasing as a flexible and • Ecosystem ready at all stage: faster than bulk powerful optimization wafer supply, design and manufacturing • Outstanding power efficiency • Very large operating range for at every level the same design • Extended IP offer • Extensive use of existing fab • Ultra-wide range DVFS • PDK is available now infrastructure • Strategic collaboration between Samsung and ST gives your SOC competitive advantages 2
7/15/2014 STNoC at a glance 5 STNoC is a hardware/software set of Services on top of a distributed on-chip network Main hardware building blocks are: Link , Router , Netw ork I nterfaces Source: Design of cost efficient Interconnect processing unit: Spidergon STNoC, STNoC tool framework: I NoC ISBN: 9781420044713 0 1.3V STNoC Architecture 6 Vana Bo Body-Bias PLL PLL ge gene nerato tor vbbn/ vbbp Network Interface ctrl regs body biased region under Varm 3
7/15/2014 STNoC: Multiple Body Biasing Regions 7 0 1.3V DDR Core A Core B DMAs GPU X DDR R AL X AL PCM AL X AL USB Video AL X X 0 1.3V 0 1.3V SATA Blitter Audio June 2014 “DRIVERS” FOR SMART CAR Presentation Title 8 Infotainment Autonomous Car Safety & ADAS EV Car2Car Car access Car2Infrastructure 4
7/15/2014 NEEDS FOR POWERFUL ENGINE 9 • Expanding senses leads to smartness, which requires big brain • Exponential increase in computing performance requirement Real time fusion of sensory multiple inputs i.e visual, radar, lidar, sensors, GPS and digital mapping Complex algorithms (Embedded Vision) for visual inputs analysis & interpretation i.e feature extraction, description, night vision… Presentation Title Multicore Architecture 10 Full Cache Coherent IO Coherent and Not Coherent Presentation Title 15/07/2014 5
7/15/2014 Dashboard Application Requirements 11 • Activation periods of real-time tasks around 2ms for the rendering and motor control, • Extreme cold boot time: system available 1.8 s after power- ‐ on • High- ‐ data throughput (through Ethernet and image processing pipe) • Low- jitter and low- ‐ latency behavior (<100ms) • Software frameworks: OpenGL ES Boot Time Optimization 12 • Speed • Optimize for target processor • Use faster medium for loading primary, secondary boot loaders and kernel. • Reduce number of tasks leading to the boot. • Remove features that are not required • Use FDSOI 6
7/15/2014 Forward Body Biasing (FBB) 13 A very reasonable effort for extremely worthwhile benefits • An extremely powerful and flexible concept in FD-SOI to : • Boost performance • Optimize passive and dynamic power consumption • Cancel out process variations and extract optimal behavior from all parts 0 1.3V FBB Vdds=-1.1, gnds=1.1 : Speed Up 14 • FBB conditions offer CMOS028 FDSOI an evident advantage in speed (100 to 150 MHz advantage at the same Vdd). • Applying FBB at the top available Vdd will provide a performance boost on the STNoC of about 23% • Target Frequency: 650 MHz • Conditions: ss_1V_125C 7
7/15/2014 Conclusions 15 • FDSOI is an innovative and cheaper technology • STNoC takes advantages from FDSOI • Faster speed • Less number of gates • Mixed Critical applications (such as Automotive ones) can get intrinsic benefits • Booting time can be reduced by 23% • Real Time support 16 Activity funded by Q A & In collaboration with Advances in FD-SOI design for power optimization June 2014 8
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