XTCA for SuperB project • FTCS • ECS Lyon Mai 2012 D.Charlet
SuperB detector SuperB detector 2 D.Charlet SuperB XTCA – CERN Lyon 0512
FCTS requirements FCTS requirements Synchronizing the experiment with the machine. Delivering and buffering the clock to the experiment. Dealing with the raw L1 trigger decision. Throttling the latter. Permits the partitioning the system into independent subsystems or groups of subsystems. Generating programmable local trigger for calibration and commissioning. Generating different commands (calibration pulse, reset, BxID and event ID). Managing the stack of IP addresses for PC farm. Keeping trace of all event-linked data to put in the event readout 3 D.Charlet SuperB XTCA – CERN Lyon 0512
Overall system achitecture Ethernet Drift Chamber L1 processor ~ 80 … Global Level1 Trigger Ethernet (GLT) Ethernet EMC L1 processor … CLK, L1, ~ 80 Raw L1 Sync Cmds ECS Detector Safety System Ethernet ctrl Ethernet ? Throttle FCTS SVT throttling Clk, L1, Sync Cmds L1 processor … … L3 to L5 Throttle FEE models ~15 Ethernet Ethernet Field Bus Clk, L1, Sync Cmds ~ 325 Radiation wall ~ 325 Crate Control Full Events Trigger primitives ROMs pre-selection FCTS interface ECS interface Event fragments Subdetector L1 Buffer Event data Tx Rx Specific Ctrl ~ 325 Optical links Electronics ~ 50 m FE Boards Detector PCs Farm FE Electronics DAQ Crate 4 D.Charlet SuperB XTCA – CERN Lyon 0512
FCTS Architecture Local trigger Clock generator Global Level module 1 trigger(GLT) L1 FCTS master : ECS FCTM FCTM 1 FCTM 2 Slow throttle FCTM 5 Fan-in / Fan-out : supports partitionning Throttle Switch FCTS Switch Front-End EMC FE IFR FE SVT FE DHC FE PID FE electronics ReadOut ReadOut ReadOut ReadOut ReadOut ReadOut Module Board Board Board Board Board Event building network 5 D.Charlet SuperB XTCA – CERN Lyon 0512
FCTS architecture push concept Fanout FEE 10 GB FCTM SWITCH Cross bar ROM Stratix V FEE Agregate FPGA NIOS ROM FCTM Fanout FEE Stratix V FPGA ROM NIOS Agregate FEE L1 Trigger RF & FID ROM Cde & Fast throttle link ROM cde dedicated link Data link ETHERNET SLOW Ethernet link TROTTLE SWITCH D.Charlet SuperB XTCA – CERN Lyon 0512
FCTS xTCA architecture Throttle switch board Standard backplane (AMC generic) channels receivers (dual star layout) ARRIA V FPGA 1 mezzanine board Switch board (Tongues 3 and 4) NIOS Control link switch board (AMC generic) channels receivers Crossbar 72 x 72 max Tongues 3 & 4 Cyclone III ARRIA V 6.5 Gbits/s PHY FPGA FPGA NIOS 1 mezzanine board SMA FCTM board (AMC) Clock distribution Tongue 2 transceiver Ethernet link 1 Gigabit Ethe transceive Stratix V FPGA Gigabit CPU Tongue 1 Ethernet Supervisio NIOS Switch mezzanine board NAT MCH (Tongues 1 and 2) 7 D.Charlet SuperB XTCA – CERN Lyon 0512
FCTS Boards ECS ECS Ip & throttle Trigger type Farm interface interface interface From farm ECS Trigger generation ECS L1 Ip destination k CCL n broadcaster i l L1 Trigger rate e r n o Fast a t Clock Controller a l p c throttle Command k i l Trottle c p a u broadcaster B d Clock Spy CCL computation Duplicator Event-linked & Data Fast serialization C ommands AMC FLASH DDR3 MMC FLASH DDR3 MMC connector @ @ Data Data Example of optical mezzanine 1 GBe link (CCPM development 2 PCIe links ECS path PCIe Clock 36 serial links Stratix V GX 8 serial links Stratix V GX Optical Mezzanine Optical Mezzanine X_FPGA path 12 serial links Throttle in, out Clock out Clock In and out TFC path Jitter Clock In @ Data Jitter PLL PLL cleaner cleaner Event buffer Event buffer DDR3 DDR3 AMC mezzanine board (CCPM development) 8 D.Charlet SuperB XTCA – CERN Lyon 0512
Control & distribution module Crate control INPUT ECS ECS ECS ECS Distributor Interface OUTPUT CLock Clock Clock Machine Clock Distributor generator L1 L1 Global Level 1 Trigger computation Distributor L1 ? Tong 1: On the shelf industrial board. Tong 2 : CCPM board 9 D.Charlet SuperB XTCA – CERN Lyon 0512
Distribution & trottle ECS ECS Interface ECS ECS Interface Emitter Tranceiver Clock To FE Tranceiver CCL duplicator Serial Clock & CCL Link Throttle Tranceiver Fast Selection Delay alignment Throttle computation To OR c ommands Serial From Commands ROM Switch (from FTCMs) Link ROMs (to FCTMs) Tranceiver computation Receiver Control Link switch module Throttle switch module AMC FLASH QDR+ MMC FLASH QDR+ MMC connector @ @ Data Data X_FPGA path 1 GBe link 1 PCIe link ECS path PCIe Clock serial links Optical or copper Optical or copper 8 serial links ARRIA V GX ARRIA V GX X_FPGA path Interface Interface 1 serial link I/O Throttle in, out Clock out Clock In and out TFC path Clock In Mezzanine AMC generic board 10 D.Charlet SuperB XTCA – CERN Lyon 0512
Open questions for FCTS • FPGA transceiver latency. • DS92Lv018 FPGA emulation. • Fast throttle link (links type, number, location,...). • Slow throttle latency (Ethernet UDP). • 2 Clocks (CCPM MCH mezzanine manage one) • FCTS crate form factor ATCA or ATCA for physics (due to the link number) – CCPM AMC and MSC mezzanine. D.Charlet SuperB XTCA – CERN Lyon 0512
ECS requirement Configuration system for individual boards located on the detector or crate located in the cavern. Located in radiation sensitive environment, up to 20KRad. Long distance link, up to 130m. Multi configuration (multi-drop bus, point to point). Multi standard interfaces (JTAG, I2C, parallel bus, ctrl I/O). Ethernet Bus Baraks Caverne SPECS SPECS Bus SPECS Slave Slave A S Serial erial P Protocol for rotocol for E Experiment xperiment C Control ontrol S System ystem SPECS SPECS A 12 D.Charlet SuperB XTCA – CERN Lyon 0512
SuperB SPECS slave implementation FPGA FPGA ProASIC3L from ACTEL. ProASIC3L from ACTEL. SPECS SLAVE MEZZANINE SPECS SLAVE MEZZANINE Triple voting register. Triple voting register. BOARD BOARD Transfer rate: ~ 14Mbits/s : ~ 14Mbits/s Transfer rate Addres Addres Addres switche switche switche Serial Serial Serial 65Kb 65Kb 65Kb prom prom prom s s s s s s s s s resonator resonator Address: Local address switch. Local address switch. Address: oscillato oscillato Broadcast address capability. Broadcast address capability. r r On board clock On board clock: Crystal resonator : Crystal resonator ChannelB[7:0 I/O / I/O / r r Connecto Connecto ] 32 32 Channel Programmable clock for SPECS read back: Programmable clock for SPECS read back: I2C I2C Loc.Addr/ Loc.Addr/ decode B Bus Bus 6 6 58mm Cd Cd & ctrl & ctrl 58mm d I2C/JTAG_DE / I2C/JTAG_DE / JTAG JTAG e e I/O I/O 12 12 Long distance capability Long distance capability: 120m cat6 cable : 120m cat6 cable Parallel Parallel Bus Bus I2C/JTAG_RE / I2C/JTAG_RE / JA JA r r Connecto Connecto 12 12 Bus Bus SPEC SPEC 2 I2C_2.5 I2C_2.5 User User Serial EEPROM Serial EEPROM: 65Kbits capacity : 65Kbits capacity V V SLAV SLAV S S I2C_3.3 I2C_3.3 I2C_3.3 2 2 2 JTAG JTAG / 4 V V V E E I2C / SPI JTAG bus, I2C bus, SPI Bus JTAG bus, I2C bus, SPI Bus PR PR -ASIC3L -ASICPlu JB JB 3 O O APA15 s 0 ds90cv01 ds90cv01 ds90cv01 APA_progra APA_progra . / . / 0 0 0 m m 7 7 RJ4 RJ4 65Lvds3 65Lvds3 65Lvds3 5 5 2 2 2 Pro Pro . . g g Connector. Connector. 82mm 82mm 13 D.Charlet SuperB XTCA – CERN Lyon 0512
Recommend
More recommend
