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.0 on xTCA DAQ working group meeting Gilles Wittwer Tuesday June - PowerPoint PPT Presentation

Oct 14, 2023 •120 likes •228 views

system .0 on xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014 DAQ block diagram PC farm DISK To other DAQ systems MUTANT BEM AGET: Asic for GET 64 analog channels - 512 cells/channel IRFU ASAD: AGET Support

  1. system .0 on xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  2. DAQ block diagram PC farm DISK To other DAQ systems MUTANT BEM AGET: Asic for GET – 64 analog channels - 512 cells/channel IRFU ASAD: AGET Support for Analog to Digital – 4 AGET CENBG COBO: COllection BOard – 4 ASAD - 1024 digital channels MSU MUTANT: MUtiplicity, Trigger ANd Time ( 3 trigger levels) GANIL BEM: Back End M odule (coupling, logical inspections, …) GANIL xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  3. Choice of µTCA standard for the project GANIL Laboratory  leader & referent for µTCA of GET « Dual Star » topology (redundancy) I2C JTAG M MMC U T J AMC13 A S AMC1 AMC12 N M CoBo T MUTANT CoBo Associated F ield R eplaceable U nits: - MicroTCA Carrier Hub (MCH) Carrier management / Network Switch - Power Module (PM) - Advance Mezzanine Card (AMC) - JTAG Switch Module (JSM) Up to 6.5 Gbit/s by serial port (1TX/1RX) - Cooling Units (CU) xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  4. Typical architecture for 1 µTCA shelf Very Front End Coupling to other DAQ or used for coupling with GTS, BUTIS …. xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  5. Full architecture – 3 µTCA shelves To GTS or BUTIS Coupling to other DAQ xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  6. What are the tasks of MUTANT ? Distribution of a 100 MHz clock to every CoBo of each crate, phase aligned (skew< 1ns - TDC)  µTCA-CLK1 Distribution of a synchronous start/stop sampling (phase aligned)  µTCA-CLK2 Exchanging data with the CoBo @ 800 Mbit/s  5 µTCA ports (TX/RX) MuTanT Building the whole TPC Digital multiplicity: Time stamp: - Master Mutant + slave MUTANT - 48 bits / 10 ns - Each MUTANT with the CoBo boards - CDT/autonomous mode every 40 ns - 32 bit event number (CDT) - local/remote (via BEM) 3 Trigger levels: -LØ= External Trigger -L1 = Multiplicity Trigger -L2 = Hit Pattern Trigger xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  7. MUTANT- CoBos data exchanges main time values AGET: Sampling Frequency = 1-100 MHz Full memory Trigger roundtrip: 512 x 10 ns = 5.12 µs to 512 x 1µs = 512 µs Event Trigger L1 MUTANT Programmable Delay & Gates are 16 bits wide Attached to GMC (10 ns) AGET Circular CoBo to MUTANT : L1: new multiplicity value @ 25 MHz max Memory nothing to do @ MUTANT level for lower frequency 512 cells L2: 1.3µs to receive the TPC hit pattern (one shelf) 12.8 µs for added shelves MUTANT trigger “OK” to CoBo “STOP”: -LØ : 30 ns/655 µs max - L1 : 80 ns /655 µs max - L2 : depends on the algorithm ! 2 x half-memories (2p decay) D_Event MUTANT information's to CoBo: - L2 mask pattern: 1.3 µs I_Event - Time stamp + Event Number: 120 ns - Time stamp only: 80 ns ½ AGET ½ AGET Circular Circular Memory Memory 256 cells 256 cells Decay Trigger (L1B) or Time-out (programmable) Implantation Trigger (L1A) xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  8. Simplified synoptic and board assembly Tongue 1 VT026 GbE Front panel AMC management RS232 Port A +Fat Pipe (Ports D,E,F,G) -V5FX30T LVDS -V5FX70T X 10 OPTICAL Tongue 3 & 4 F To BEM buffers transceivers (200 signals) L (Optical link) ICE ribbon fibbers A MUTANT E LVDS/ S Master/Slave FLASH M TRIGGER & LVPECL H Front panel C buffers TIME STAMPER VHDCI link D ENGINE D NECL R CENTRUM/SCALERS DDR2 Front panel Interface buffers 2 B A TRIGGER I/O Global Master Clock buffers TDC Front panel Interface Management/Distribution Front panel Tongue 2 Board B TONGUE 4 3 2 1 1 tongue = 2 x 85 pins Board A 4 tongues to manage = 680 pins! xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  9. GANIL is also in charge of µTCA solution validation for GET project  2 sources of µTCA shelf are validated for the project - a “9 AMC slot” shelf & an “11 AMC slot + JSM” shelf  2 sources of MCHs with 10 Gbe uplink were purchased - Used in a first step for management and tests - Network performance tests have to be made  1 source of JTAG Switch module is validated - JSM 008 from Vadatech xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

  10. Conclusion B A - MUTANT: full production based on 2 runs (autumns 2014 and 2015) 1 module (2 boards) - CoBo boards available from Vadatech (ECRIN) - ASAD boards available from FEDD (France) (Caen, Saclay, Bordeaux) First users through the world (Michigan, Texas) (with new TPC, Si detectors,…) (Catania) (Riken, JPARC) (Daejeon) xTCA DAQ working group meeting Gilles Wittwer Tuesday June 10, 2014

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