www.xs3d.kaist.ac.kr/ismi2015/ Simulation Based Experimental - PowerPoint PPT Presentation

ISMI 2015 International Symposium on Semiconductor Manufacturing Intelligence 16 th – 18 th October 2015, Daejeon, South Korea www.xs3d.kaist.ac.kr/ismi2015/

Simulation Based Experimental Investigation for Performance Assessment of Scheduling Policies in Wafer Fabrication Rashmi Singh 1 , M. Mathirajan 2 Indian Institute of Science, Bangalore, India Email Id: - rashmi@mgmt.iisc.ernet.in

Outline of the presentation Introduction  Literature Review  Research Objective  Simulation Model for Mini Fab  Experimental Design  Experimentation and Analysis  Conclusions and Future Research 

Introduction Global impact of semiconductor industry - from a worldwide base semiconductor market of US$ 226  billion in 2009, the industry enables the generation of electronics systems and services, which account for about 10% of the total world GDP. Service Providers – telecom operators, broadcast, internet service providers etc. Automobile, industrial, defense, medical, space Electronics (USD 1,750 billion) Accounts for about 10% of Semiconductors the world GDP USD 226 billion Source: Worldwide Semiconductor Trade Statistics (WSTS), IMF, European Semiconductor Industry Association (ESIA) Competitiveness Report, 2009

Contd … Cyclical nature of global semiconductor industry - industry is research- and development-intensive at  the design stage and capital-intensive during the manufacturing phase. This is accompanied by continuous growth in a cyclical pattern with high volatility. Generally, cycles include an expansion and peak period, followed by a slowdown phase, and eventually a  downturn stage. This industry has witnessed six major cycles since 1970, and there is good reason to believe that 2009 marked  the end of the downturn phase of another cycle. Downturn phase Expansion and 1-2 years of flat peak phase 2-3 or declining years of strong phase (20%) growth Slowdown phase Source: EY research 2010

Contd … Split of semiconductor revenues by segment, 2015 –  Discrete Semiconductors – transistors, diodes, etc purpose of which is switching, amplifying and transmitting electrical signals (quite stable due to lower presence in computer applications). Optoelectronics – electrical or optical transducers Sensors – sense physical quantity and convert it to electrical signals Integrated circuits – miniaturize electronic circuits (integrating a large number of tiny transistors into a small chip). It includes analog (14%), memory (20%), micro (21%) and logic (29%) components. Revenues 6% Integrated Circuits (84%) 2% 8% Sensors (2%) Optoelectronics (8%) Discrete (6%) 84% Source: Worldwide Semiconductor Trade Statistics (WSTS)

Contd … Indian semiconductor industry overview - India is playing a major and increasing role in the global  electronics industry, which motivates the development of a local semiconductor manufacturing base. The global electronics industry is very large and growing. India’s electronics industry is already important and  growing at 7x the global rate India market currently represents ~2% of the global production of electronics and is expected to grow at 22% per  year Global production of electronics, 2004-2020E$ Trillions  3 2.5 2 1.5 1 0.5 0 2004 2009 2014E 2020E India has around $7 billion in annual semiconductor consumption and the import burden driven by this disparity  will grow significant by 2020 to $45-50 billion. India has a significant human capital presence already in semiconductors, but is currently focused on design. With  a large talent pool of 200K+ design engineers, India semiconductor design market has grown at 28% over the last 7 years Source: ESDM DOIT report, NSF, Study on semiconductor design embedded software and services industry and IC economics report

Motivation Very expensive equipment ($200K - $14M) and very expensive clean rooms (<$3K per sq.ft.)  28% price increases of equipment per year  Equipment purchases account for 70%-80% of capital expenditure in new fabs  Cost of new fabs is doubling every 3 years  Revenue opportunity/wafer is ($5000 - $12,500)  World Semiconductor Trade Statistics (WSTS) anticipates the semiconductor revenue to rise steadily from  2013 ($306 billion) total to $325 billion this year, $336 billion in 2015 to reach $350 billion by 2016. National Democratic Alliance (NDA) government’s flagship ‘Make in India’ programme, the centre plans to  spend 10 billions of dollars to put in place an ecosystem for electronics manufacturing in the country. Implementation of an improved control strategies could result in a considerable amount of increased profits  because the capital investment and sales revenue of wafer fab are extremely large. http://www.informatik.uni-rostock.de/~lin/GC/Slides/Fowler.pdf http://www.forbes.com/sites/jimhandy/2014/06/26/wsts-updates-semiconductor-forecast-325-billion-in-2014/ http://www.livemint.com/Industry/ZRBFOTaucH1NO9el7JLZXJ/Govt-to-invest-10-billion-in-two-computer-chipmanufacturin.html

Types of Research in Wafer fabrication Wafer fabrication Preventive Material Process Scheduling Plant Layout Maintenance Handling Capability Mask Batch Release Dispatching Scheduling Scheduling Control

Literature Review in Wafer Fabrication Release Model Characteristics References Policies Immediate No breakdown or manpower limitation, Ragatz and Mabert [1988], Bobrowski and Release (IMR) Poisson (mean rate is 1.0728 per hr), Park [1989], Ahmed and Fisher [1992], Kim exponential processing time (1-4hr). et al [1996], Rose ([1999] & [2001]) Random Release No rework, no set-ups time, no batch Ragatz and Mabert [1988], Bobrowski and (RAND) process, neither operators nor Park [1989] transporters are modeled. Constant Release Single product, hypothetical fab, batch Wein [1988], Glassey and Resende [1988], (CONST) process is not considered. No rework, Gilland [2002] and Lin et al [2007], Glassey no set-ups time, no batch process, et al. [1996], Chern and Huang [2004], Lou neither operators nor transporters are and Kager [1989], Kim et al [1996] modeled. Workload Single product, machine breakdown Wein [1988], Glassey and Resende [1988], Regulating (WR) considered are not standard, throughput Glassey et al. [1996], Chern and Huang time and compared (RAND, CONST, [2004], Rose [1999] & Kim et al [1996] CONWIP and WR), processing times include set-ups, operator unavailability and rework and no batch process.

Contd … Release Policies Model Characteristics References Starvation Avoidance (SA) Single product, hypothetical fab, batch process is Glassey and Resende [1988] not considered, trade-off curve and compared (CONST, WR, CONWIP & SA) using SRPT & FIFO. Descending Control (DEC) No yield loss, all machines are available all the Glassey et al. [1996] time, set-ups are negligible and used exponential processing time. Compared (CONST, CONWIP, WR & DEC). Adaptive in MTO situations. Constant Work-in-process No rework, no set-ups time, no batch process, Spearman et al [1990], Glassey and (CONWIP) neither operators nor transporters are modeled. Resende [1988], Wein [1988], Glassey et al. [1996], Chern and Huang [2004], Rose ([1999] & [2001]) Workload Regulated Batch- No yield loss, single product, neither operators Chern and Huang [2004] sizing rule or (k, w) rule nor transporters are modeled, no travel time is considered. Compared with (CONST, CONWIP, WR & (k, w)).

Contd … Release Policies Model Characteristics References Constant Load No yield loss, no rework, neither operators nor Rose [1999] (CONLOAD) transporters are modeled, set-ups are negligible & compared with (IMR, CONWIP, WR & CONLOAD). Total Cycle Time No yield loss, no rework, neither operators nor Rose [2001] (TOTAL CT) transporters are modeled, set-ups are negligible & compared with (IMR, CONWIP, CONLOAD & TOTAL CT). Flow Rate Control Policy No rework, no set-ups time, no batch process, Lou and Kager [1989] (FRCP) neither operators nor transporters are modeled. Compare with (CONST & FRCP). Dynamic Release Control No rework, no set-ups time, no batch process, Kim et al [1996] Policy (DRCP) neither operators nor transporters are modeled. no travel time is considered. Compared with (CONST, IMR, WR & DRCP)

Literature Review in Wafer Fabrication Scheduling Policies Control References Configuration Release Immediate Release Open-Loop Closed Ahmed and Fisher [1992], Wein [1988], Arisha et Policies (IMR), Random Release Release Policies al. [2003], Glassey and Resende [1988], Glassey (RAND) and Uniform et al. [1996], Release (UNIF) SA, WR, PWR, Closed-Loop Closed Wein [1988], Glassey and Resende [1988], CONLOAD, TOTAL CT, Release Policies Glassey et al. [1996], Kim et al [1996] , Kim et al (k, w), FRCP, CONWIP, [1998] , Kim et al [2001] , Gilland [2002] , Chern HPSRC, DEC, DRCP, and Huang [2004] , Qi et al [2009], Khaled and Ei- D-Roll, WIPLCtrl, EWP, Kilany [2011], Tabatabaei and Salazar [2011], Lou and Kager [1996], and Huang [2004] , Qi et al [2009], Khaled and Ei-Kilany [2011], Tabatabaei and Salazar [2011] Dispatching FIFO, LIFO, SIPT Simple Rules Wein [1988], Glassey and Resende [1988], Glassey et al. [1996], Kim et al [1996] , Kim et al [1998] , Kim et al [2001], Chern and Huang [2004] , Qi et al [2009], Khaled and Ei-Kilany [2011], Tabatabaei and Salazar [2011], Lou and Kager [1996], and Huang [2004] , Qi et al [2009], Khaled and Ei-Kilany [2011], Tabatabaei and Salazar [2011]