VLSI Testing Automatic Test Pattern Generation Virendra Singh Associate Professor C omputer A rchitecture and D ependable S ystems L ab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in EE-709: Testing & Verification of VLSI Circuits Lecture 10 (4 Feb 2013) CADSL
TG using BDDs (1/4) Reduced Graph x 1 g x 1 x 2 ( x 1 + x 2 )· x 3 f x 2 x 3 x 3 0 1 Trace a path from the root to 0 and 1 Value of the variables other than fault should have same value TP for s-a-0 fault at x 1 is x 1 x 2 x 3 = 101 TP for s-a-1 fault at x 1 is x 1 x 2 x 3 = 001 04 Feb 2013 EE-709@IITB 2 CADSL
TG using BDDs (2/4) ∧ ∨ ∧ ∨ ∧ ( a b ) ( a b ) ( a b ) 1 1 2 2 3 3 a 1 a 1 p b 1 b 1 a 2 q f a 2 b 2 b 2 a 3 r a b 3 3 b 3 s-a-0 at a 1 0 1 a 1 =1, b 1 =1, a 2 =0, a 3 =0 04 Feb 2013 EE-709@IITB 3 CADSL
TG using BDDs (3/4) ∧ ∨ ∧ ∨ ∧ ( a b ) ( a b ) ( a b ) 1 1 2 2 3 3 a 1 a 1 p SA0 b 1 b 1 a 2 q f a 2 b 2 b 2 a 3 r b 3 a 3 b 3 s-a-0 at p 0 1 a 1 =1, b 1 =1, a 2 =0, a 3 =0 04 Feb 2013 EE-709@IITB 4 CADSL
TG using BDDs (4/4) ∧ ∨ ∧ ∨ ∧ ( a b ) ( a b ) ( a b ) 1 1 2 2 3 3 a 1 a 1 p b 1 b 1 a 2 q f a 2 b 2 b 2 a 3 r b 3 a 3 b 3 s-a-0 at q 0 1 a 2 =1, b 2 =1, a 1 =0, a 3 =0 04 Feb 2013 EE-709@IITB 5 CADSL
ATPG - Algorithmic Path Sensitization Method Fault Sensitization Fault Propagation Line Justification Path Sensitization Algorithms D- Algorithm (Roth) PODEM (P. Goel) FAN (Fujiwara) SOCRATES (Schultz) SPIRIT (Emil & Fujiwara) 04 Feb 2013 EE-709@IITB 6 CADSL
Path Sensitization General Structure of TG Algorithm begin set all values to x Justify (l, v) if (v = 0) then Propagate (l, D) else Propagate (l, D’) end 04 Feb 2013 EE-709@IITB 7 CADSL
Path Sensitization Justify( l, val) begin set l to val if l is a PI then return /* l is a gate output */ c = controlling value of l i = inversion of l inval = val ⊕ i if (inval = c’) then for every input j of l Justify (j, inval) else select one input ( j ) of l Justify (j, inval) end 04 Feb 2013 EE-709@IITB 8 CADSL
Path Sensitization Propagate (l, err) /* err is D or D’ */ begin set l to err if l is PO then RETURN k = fanout of l c = controlling value of k i = inversion of k for every input of j of k other than l Justify ( j, c’ ) Propagate ( k, err ⊕ i ) end 04 Feb 2013 EE-709@IITB 9 CADSL
Path Sensitization Justify (a, 1) Justify (d, 1) 1 D D’ Propagate (d, D) Justify (b, 1) Propagate (f, D’) SA0 D’ 1 0 1 Justify (e, 0) Justify (c, 1) 04 Feb 2013 EE-709@IITB 10 CADSL
Common Concept Fault Activation problem a LJ Problem The Fault Propagation problem 1. Select a FP path to PO Decision 2. Once the path is selected a set of LJ problems The LJ Problems Decisions or Implications To justify c = 1 a = 1, b = 1 (Implication) To justify c = 0 a = 0 or b = 0 (Decision) Incorrect decision Backtrack Another decision 04 Feb 2013 EE-709@IITB 11 CADSL
D-Algorithm Roth (IBM) - 1966 Fundamental concepts invented: – First complete ATPG algorithm – D-Calculus (5 valued logic) – Implications – forward and backward – Implication stack – Backtrack – Test Search Space 04 Feb 2013 EE-709@IITB 12 CADSL
Decisions during FP 0 D’ 1 0 D’ 1 1 D’ 1 0 1 0 D – frontier: The set of all gates whose output value is currently x but have one or more fault signals on their inputs 04 Feb 2013 EE-709@IITB 13 CADSL
Decisions during LJ 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 D’ 0 0 0 1 D’ 1 D’ D’ J – Frontier : A set of all gates whose output value is known but not implied by its input value 04 Feb 2013 EE-709@IITB 14 CADSL
Implications (Forward) 04 Feb 2013 EE-709@IITB 15 CADSL
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