Virtual Memory and I/O Lecture 27 CS301 I/O I/O Transfer of data - PowerPoint PPT Presentation

Virtual Memory and I/O Lecture 27 CS301

I/O

I/O • Transfer of data to/from any component other than main memory w Memory frequently at one end of the transfer • Today’s systems frequently limited by I/O performance, not CPU • Usually talk about bandwidth for performance w How much data we can transfer in one time unit w How many I/O operations we can complete in one time unit • Response time sometimes talked about as well

Example Hardware w/ I/O Interrupts Processor $ Memory-I/O Bus I/O controller I/O Controller I/O Controller Main Memory Graphics Network Disk Disk Output

Example I/O Devices • Disk • Monitor • Keyboard • Network • Mouse • Printer • Speakers

I/0 is Complex

Basic Organization • Bus connects many I/O devices to processor/memory • Devices connect to bus via controller

Buses • Connect I/O Devices to Processor and Memory • Shared communication resource (broadcast medium) w Connect multiple components together w Only one entity can send at a time w All components simultaneously listen • Pro: w Cheap w Easy to add new devices • Con: w Sharing of resource can create contention which limits maximum data sent w Speed limited by length and number of devices

Buses • Composed of w Control lines – Signal requests and acknowledgements, indicate what type of data on data lines w Data lines – Carry real data or addresses § Each line contains one bit • You want lots of these § Sometimes there are separate data and address lines

Types of Buses Processor-memory bus Main Processor Memory Bus adapter I/O controller Disk I/O bus I/O controller Disk • Processor-Memory Buses w Short w High speed w Matched to memory system to maximum P/M bandwidth

Types of Buses • I/O Buses w Long w Many devices w Devices vary considerably in bandwidth capabilities w Often connect to memory via P/M or backplane bus w Example: SCSI

Types of Buses Backplane bus Main Processor Memory I/O controller I/O controller Disk Disk • Backplane Buses w Enable processors, memory, and I/O devices to coexist on same bus w Part of chassis that all components are attached to

Types of Buses Proprietary • Processor-Memory Buses w Short w High speed w Matched to memory system to maximum P/M bandwidth • I/O Buses Standardized w Long (Ex. PCI) w Many devices w Devices vary considerably in bandwidth capabilities w Often connect to memory via P/M or backplane bus • Backplane Buses w Enable processors, memory, and I/O devices to coexist on same bus

Interface to/from I/O • How does CPU tell I/O what to do? • Special purpose instructions (Programmed I/O) w There are instructions in ISA for talking to I/O devices w Con: Hard to anticipate all of the different devices that may exist in future • Memory-mapped I/O w Subset of address space reserved for I/O device registers. Communication uses normal ld/st instructions to write to these special memory locations

Memory Mapped I/O • Commands issued to devices via normal memory writes to special memory locations w Memory system ignores operation because addresses are for I/O w Device controller sees write to addresses associated with its device, records the data, transmits data to device as a command w Data returned to memory using normal memory read instructions to special addresses w Special addresses only accessible by OS

Device Driver Plug-in to OS • Acts as bridge between the OS's hardware abstraction layer • and the physical device Allows you to issue commands like • w open() w close() w read() w write() without worrying what kind of disk you have Translates these commands into (possibly standardized) • commands for device.

Device Controller • Interprets high-level commands (possibly some standard) received from I/O interface into series of device specific actions (electrical signals) w High level command: write this block w Low-level operations: position head over disk track, write data inside track • Converts and interprets electrical signals received from device and modifies value of status register

Interface to/from I/O • How does I/O device tell CPU something? • Polling - CPU checks each device periodically w Simple w CPU does needless work when no devices need attention w Ready devices have to wait for idle devices to be polled • Interrupt-driven I/O - devices send signal to CPU that interrupts CPU w Interrupts occur asynchronously with respect to instruction execution w Interrupt signal should include identity of device that generated it w CPU other wise free to do real work

Example Disk Write • Program places data in memory buffer belonging to OS and makes system call w Syscall includes device, buffer address, # bytes • CPU sends first word of data to be transferred to data register on disk controller • CPU sends write command to disk controller • Write operation completed by controller. Generates interrupt. • CPU runs interrupt handler which checks if there is more data to write. If so, repeats (all but first step)

Direct Memory Access (DMA) • Sending 1 word at a time is slow and wasteful of processor cycles • DMA allows transfer of entire block of data without direct CPU involvement w Special DMA controller must exist on bus • Steps for DMA: w CPU sets up DMA controller with device #, operation, starting address, and # bytes w DMA controller starts transfer, generating new device requests when needed w CPU interrupted when entire procedure done

HW/OS Interface • Syscall w Allows user to ask OS to do stuff • Exception w Unexpected event from within the processor w Example: Arithmetic Overflow • Trap/Fault w Type of exception that usually can be handled easily and execution can continue w Example: Page fault • Interrupt w Unexpected event from outside of the processor w Example: I/O device request