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What is a bus? A Bus is: a shared communication link Slow vehicle - PDF document

Oct 04, 2023 •229 likes •311 views

What is a bus? A Bus is: a shared communication link Slow vehicle that many people ride together a single set of wires used to connect multiple subsystems well, true... A bunch of wires... Processor Input Control Memory

  1. What is a bus? A Bus is: ■ a shared communication link ■ Slow vehicle that many people ride together ■ a single set of wires used to connect multiple subsystems – well, true... ■ A bunch of wires... Processor Input Control Memory Datapath Output ■ a Bus is also a fundamental tool for composing large, complex systems – systematic means of abstraction Datorteknik F1 bild 1 Datorteknik F1 bild 2 Advantages of Buses Disadvantage of Buses I/O Device I/O Device I/O Device Memory Processor I/O Device I/O Device I/O Device Memory Processor ■ It creates a communication bottleneck ■ Versatility: – The bandwidth of that bus can limit the maximum I/O throughput – New devices can be added easily ■ The maximum bus speed is largely limited by: – Peripherals can be moved between computer systems that use the same bus standard – The length of the bus ■ Low Cost: – The number of devices on the bus – The need to support a range of devices with: – A single set of wires is shared in multiple ways ■ Widely varying latencies ■ Manage complexity by partitioning the design ■ Widely varying data transfer rates Datorteknik F1 bild 3 Datorteknik F1 bild 4 The General Organization of a Bus Master versus Slave Master issues command Bus Bus Control Lines Data can go either way Master Slave Data Lines ■ A bus transaction includes two parts: ■ Control lines: – Issuing the command (and address) – request – Signal requests and acknowledgments – Transferring the data – action – Indicate what type of information is on the data lines ■ Master is the one who starts the bus transaction by: ■ Data lines carry information between the source and the – issuing the command (and address) destination: ■ Slave is the one who responds to the address by: – Data and Addresses – Sending data to the master if the master ask for data – Complex commands – Receiving data from the master if the master wants to send data Datorteknik F1 bild 5 Datorteknik F1 bild 6

  2. Example: Bus Types of Buses Architecture ■ Processor-Memory Bus (design specific) Processor/Memory Bus – Short and high speed – Only need to match the memory system ■ Maximize memory-to-processor bandwidth – Connects directly to the processor – Optimized for cache block transfers Backplane Bus ■ Backplane Bus (standard or proprietary) – Backplane: an interconnection structure within the chassis – Allow processors, memory, and I/O devices to coexist – Cost advantage: one bus for all components I/O Busses ■ I/O Bus (industry standard) – Usually is lengthy and slower – Need to match a wide range of I/O devices – Connects to the processor-memory bus or backplane bus Datorteknik F1 bild 7 Datorteknik F1 bild 8 Example: Motherboard Abit BH6 A Computer System with One Bus: Backplane Bus Backplane Bus Processor Memory I/O Devices ■ A single bus (the backplane bus) is used for: – Processor to memory communication – Communication between I/O devices and memory ■ Advantages: Simple and low cost ■ Disadvantages: slow and the bus can become a major bottleneck ■ Example: IBM PC - AT Datorteknik F1 bild 9 Datorteknik F1 bild 10 A Two-Bus System A Three-Bus System Processor Memory Bus Processor Memory Bus Processor Memory Processor Memory Bus Bus Bus Bus Adaptor Adaptor Adaptor Adaptor Bus I/O I/O I/O Adaptor I/O Bus Backplane Bus Bus Bus Bus Bus I/O Bus Adaptor ■ I/O buses tap into the processor-memory bus via bus adaptors: – Processor-memory bus: mainly for processor-memory traffic ■ A small number of backplane buses tap into the processor- – I/O buses: provide expansion slots for I/O devices memory bus ■ Apple Macintosh-II – Processor-memory bus is used for processor memory traffic – NuBus: Processor, memory, and a few selected I/O devices – I/O buses are connected to the backplane bus – SCSI Bus: the rest of the I/O devices ■ Advantage: loading on the processor bus is greatly reduced Datorteknik F1 bild 11 Datorteknik F1 bild 12

  3. Processor-Memory Bus Memory Bus ■ This bus connects the CPU to RAM 4*32 – Designed for maximal bandwidth Each access 00xx 01xx 10xx 11xx transfers 128 bits – Usually wide, 32 bits or more – To further increase bandwidth we use a Cache – Burst access between cache and memory, early restart Cache Miss STALL, Start Burst read from RAM PA[3:2] 1 32 Each RAM bank 00xx 01xx 10xx 11xx Release Pipe STALL is only accessed Continue Burst read from RAM every fourth cycle PA[3:2] on “burst read” 4 2 3 Datorteknik F1 bild 13 Datorteknik F1 bild 14 What defines a bus? On Chip Cache (1st level) CP0 Using separate Instruction and Data Transaction Protocol caches, we can read a Hit simultaneously IM DE EX DM for both Instruction and Data Timing and Signaling Specification In this model 1st level caches use virtual address, and must pass TLB on Cache miss Bunch of Wires • 1st level cache must be fast Instr Data • Limited area on chip Cache Cache Electrical Specification • Usually 8-64 kb Physical / Mechanical Characterisics – the connectors Datorteknik F1 bild 15 Datorteknik F1 bild 16 Synchronous and Asynchronous Bus Synchronous Bus ■ Synchronous bus: – Includes a clock in the control lines ■ A single clock controls the protocol – A fixed protocol for communication that is relative to the clock – Pros – Advantage: involves very little logic and can run very fast ■ Simple (one FSM) – Disadvantages: ■ Fast ■ Every device on the bus must run at the same clock rate – Cons ■ To avoid clock skew, they cannot be long if they are fast ■ Clock skew limits bus length ■ Asynchronous bus: ■ All devices work on the same speed (clock) – It is not clocked ■ Suitable for Processor-Memory Bus – It can accommodate a wide range of devices – It can be lengthened without worrying about clock skew – It requires a handshaking protocol Datorteknik F1 bild 17 Datorteknik F1 bild 18

  4. Asynchronous Bus Asynchronous Protocol ■ Uses a handshaking to implement a ■ ReadReq transaction protocol ■ DataReady Master Slave ReadReq – Pros ■ Ack Ack ■ Versatile, generic protocols ■ Dynamic data rate Wait for Data – Cons ■ More complex, two communication FSMs ■ Slower, (but usually can be made quite fast) DataReady Ack Datorteknik F1 bild 19 Datorteknik F1 bild 20 Busses so far Bus Transaction Master Slave ° ° ° Control Lines ■ Arbitration Address Lines ■ Request Data Lines ■ Action Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Bus Transfers: sequence relative to common clock. Datorteknik F1 bild 21 Datorteknik F1 bild 22 Arbitration: Obtaining Access to the Bus Bus Arbitration Control: Master initiates requests Bus Bus Data can go either way Master Slave ■ Bus Master, (initiator usually the CPU) ■ Slave, (usually the Memory) ■ One of the most important issues in bus design: – How is the bus reserved by a devices that wishes to use it? Arbitration signals ■ Chaos is avoided by a master-slave arrangement: – Only the bus master can control access to the bus: ■ BusRequest It initiates and controls all bus requests ■ BusGrant – A slave responds to read and write requests ■ BusPriority ■ The simplest system: – Higher priority served first – Processor is the only bus master – Fairness, no request is locked out – All bus requests must be controlled by the processor – Major drawback: the processor is involved in every transaction Datorteknik F1 bild 23 Datorteknik F1 bild 24

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