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Apr 09, 2023 •440 likes •709 views

2003 International Test Conference DESIGN CONSIDERATIONS IN USING 1149.1 AS A BACKPLANE TEST BUS Pete Collins petec@jtag.co.uk JTAG TECHNOLOGIES BTW03 BTW03 Presented By Stephen Harrison & Peter Collins PURPOSE The purpose of this

  1. 2003 International Test Conference DESIGN CONSIDERATIONS IN USING 1149.1 AS A BACKPLANE TEST BUS Pete Collins petec@jtag.co.uk JTAG TECHNOLOGIES BTW03 BTW03 Presented By Stephen Harrison & Peter Collins

  2. PURPOSE The purpose of this presentation is to discuss the importance of correctly identifying the system test requirements at the design concept stage so that the optimal system test access architecture is implemented. This is because:- � Hierarchical IEEE Std. 1149.1 backplane test access has become increasingly accepted as a test strategy for testing boards/modules within a system environment. � The emergence of a variety of 1149.1 system test access devices from a number of silicon vendors now provides designers with more choice. � System level architectural requirements dictate what system test access devices should be used. Presented By Stephen Harrison & Peter Collins

  3. CONTENT Introduction � � System Level Routing Strategies � Supporting Devices � Architectural Decisions Embedded Vector Delivery � � BIST Sequencer Overview � Board & System Level BIST Strategy � Conclusions Presented By Stephen Harrison & Peter Collins

  4. INTRODUCTION Implementation of a system level test architecture can be utilised to provide a more flexible test and enhanced diagnostic capability by:- Providing a single-point access to multiple scan chains in support � of design and test partitioning. Support a board-to-board interconnect test strategy that will allow � edge connector pin level diagnosis. Accommodate system checkout of firmware objects prior to customer � shipment and facilitate field level firmware upgrades. Provide a system level infrastructure to exercise embedded test � structures implemented within ASIC’s and FPGA’s. Presented By Stephen Harrison & Peter Collins

  5. System Architecture ( Star ) Board 2 Board N Board 1 Board 3 TDI TDO TCK TRST TMS(1) TMS(2) TMS(3) TMS(N) Multiple TMS lines significantly increases backplane signalling Presented By Stephen Harrison & Peter Collins

  6. System Architecture ( Ring ) Board 3 Board N Board 2 Slot Empty Board 1 Breaks TDO/TDI Chain TDI TDO TCK TRST TMS Boundary Scan cannot be performed due to empty slot which breaks the boundary scan chain Presented By Stephen Harrison & Peter Collins

  7. System Architecture ( Multi-drop ) Board 1 Board 2 Board N Board 3 System System System System Access Access Access Access device device device device Slot ID Slot ID Slot ID Slot ID TDI TDO TCK TRST TMS Backplane access limited to the 5 JTAG control signals + 6 address lines for selecting the board slot ID Each board requires the minimum of a single System Interface device Presented By Stephen Harrison & Peter Collins

  8. Hierarchical Boundary-Scan System Access A system level device contains one primary TAP and one or � more secondary TAP’s. � The local board boundary-scan chains are connected to the secondary TAP’s. � The boundary-scan controller is connected to the primary TAP. By applying the appropriate system level device protocol, the � primary TAP of the device can access the chains on the secondary TAP’s Secondary (Local) Primary TAP1 (Global) System Boundary-scan Access TAP2 Controller TAP1 Device TAP3 Presented By Stephen Harrison & Peter Collins

  9. System Level Configuration External Controller Printed Circuit Board 1 Printed Circuit Board 2 Scan Chain 3 Scan Chain 2 Printed Circuit Board 3 Scan Chain 3 Scan Chain 1 Scan Chain 2 Scan Chain 3 Printed Circuit Board n Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 1 Scan Chain 2 Device Flash Scan Chain 1 Device Flash Device Device Flash External Device Device Flash Device Device JTAG Controller Device Device TDI 1 TMS 1 TCLK 1 TDO 1 Device Auto-Write 1 External Scan TDI 1 TMS 1 TCLK 1 TDO 1 ScanBridge Device Control Auto-Write 1 TDI 1 TMS 1 External Scan TCLK 1 TDO 1 ScanBridge Auto-Write 1 Control Board ID Tracking External Scan Board ID Register TDI 1 ScanBridge TMS 1 TCLK 1 TDO 1 Control Auto-Write Slot ID Board ID Tracking Auto-Write 1 External Scan Board ID Register ScanBridge Auto-Write Slot ID Board ID Tracking Control Board ID Register Auto-Write Slot ID Board ID Tracking Board ID Register Auto-Write Slot ID Slot ID TDI, TDO, TMS Standard TRST, TCLK & AW Backplane I/O Presented By Stephen Harrison & Peter Collins

  10. System Level Configuration Embedded Controller Printed Circuit Board 1 Printed Circuit Board 2 Scan Chain 3 Scan Chain 2 Scan Chain 3 Printed Circuit Board 3 Scan Chain 1 Scan Chain 2 Scan Chain 3 System Controller Card Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 1 Scan Chain 2 Device Flash Scan Chain 1 Device Flash Device Device Flash Device Device Device ASIC Flash Device TDI 1 TMS 1 TCLK 1 TDO 1 Device Auto-Write 1 External Scan FPGA Up TDI 1 TMS 1 TCLK 1 TDO 1 ScanBridge Control Auto-Write 1 External Scan TDI 1 TMS 1 TCLK 1 TDO 1 ScanBridge Control Auto-Write 1 Board ID Tracking Board ID Register External Scan TDI 1 TDO 1 ScanBridge Board ID Auto-Write Slot ID Tracking Control Auto-Write 1 Board ID Register ScanBridge & External Scan Auto-Write Slot ID Control Board ID Tracking Scan Controller Board ID Register Board ID Auto-Write Slot ID Tracking Board ID Register Auto-Write Slot ID Slot ID TDI, TDO, TMS Standard TRST, TCLK & AW Backplane I/O Presented By Stephen Harrison & Peter Collins

  11. Types of System Level Devices Chipset Solution Providers Chipset Solution Providers Device Name Semi-house JTS03 (IP Core or as device) Gateway Device Firecron Ltd Firecron Ltd Gateway Device JTS06 (IP Core or as device) SCANSTA111 ScanBridge National Semiconductor SCANSTA112 ScanBridge National Semiconductor LSC BSCAN-1 Lattice Semiconductor Multiple Scan Port Lattice Semiconductor Scan Path Linker LSC BSCAN-2 Texas Instruments SN54/74LVT8996 Addressable Scan Port SN54/74ACT8997 Scan-Path Linker Texas Instruments SN54/74ACT8986 Linking Addressable Scan Port Texas Instruments Chipset Features � How many local scan ports are supported ? � Does the system test access device support Multidrop access ? � Does the system test access device support parking of local scan chains ? � Is there provision to access proprietary test signals ? � Does the system test access device have a generic pass through capability ? � Does the system test access device have the capability to read back the board ID and Revision ? Presented By Stephen Harrison & Peter Collins

  12. Multidrop Test Configuration Primary Board 1 1 LSC1 Tester TAP1 Boundary-scan 2 ScanBridge LSC2 Controller 3 MULTIDROP 1 (STA111) 4 No Chain Board 2 LSC1 Gateway LSC2 Device LSC3 MULTIDROP 2 (JTS03) Gateway LSC3 Device LSC4 No Chain (JTS03) Presented By Stephen Harrison & Peter Collins

  13. Proprietary Test Signal Pass-through � Dependant upon specific board designs it may be necessary to route proprietary test signals from the edge connector to devices within the target local scan chain i.e. passing-through a WE Strobe pulse to optimise flash programming. � This can be a generic pass-through capability i.e. input-to-output or dependant on local scan chain selection. This is important when the local distribution of the proprietary signal is to multiple chains and devices. cPLD WE WE Gateway/Bridge WE LSC 1 Address MPC8260 Flash Data JTAG Bus LSC 1 Primary Memory Processor Scan Port Control WE LSC 2 N/C DSP JTAG Bus LSC 2 WE Strobe WE LSC 3 N/C ASIC JTAG Bus LSC 3 Presented By Stephen Harrison & Peter Collins

  14. Transparent Mode � Vendor specific proprietary programming/emulation tools P/Thr P/Thr P/Thr do not support the protocols necessary to communicate Sel(0) Sel(1) Enable with system access devices. LSC 1 1 0 0 � Generic pass-through capability necessary to make the LSC 2 0 1 0 connection between primary JTAG port and LSP transparent LSC 3 1 1 0 by dedicated control pins or specific instruction. X X 1 HIGHZ 0 0 0 Gateway/Bridge TRANSPARENTn FPGA’s Pass/Thru on LSP 1 Primary JTAG Port DSP Pass/Thru on LSP 2 0 Pass/thru Enable Pass/thru Sel 0 0 cPLD’s Pass/Thru on LSP 3 Pass/thru Sel 1 1 Presented By Stephen Harrison & Peter Collins

  15. How do I Read the Board ID and Revision? � Gateway devices have an internal 16-bit Register which can be hard-coded by tying device pins to Vcc or GND dependant upon user-defined ID code. This register can be accessed once the Gateway is selected. � Alternative devices do not have this utility, subsequently a set LSC on each card within the system will need to dedicate this LSC and 1149.1 compliant device to hard-wire the board ID code and revision i.e. cPLD or Scan buffer. � The limitations in this alternative method is that board designs are subject to change due to obsolescence etc. that may change the boundary-scan infrastructure. Gateway/Bridge JTAG Bus LSC 1 cPLD Primary Scan Port Hard-wire unused I/O pins To VCC or GND to provide User-definable ID code BOARD_ID Register 16-bit User-definable Register hard-wired to Vcc or GND Depending upon ID code Presented By Stephen Harrison & Peter Collins

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